| Message ID | 166067375099.1614719.8244364251253955254.stgit@djiang5-desk4.jf.intel.com |
|---|---|
| State | Under Review |
| Delegated to: | Dan Williams |
| Headers | show |
| Series | [1/2] cxl: export interleave address mask as port sysfs attribute | expand |
Dave Jiang wrote: > Export the interleave address mask as a sysfs attribute for a port. The > interleave address mask is created based off the CXL HDM Decoder Capability > Register (CXL spec v3 8.2.4.19.1) and sets the bits indicated by th "A11to8 > Interleave Capable" bit and the "A14to12 Interleave Capable" bit. It > indicates the decoder supports interleaveing based on those address bits. > The exported sysfs attribute will help user region creation to do more valid > configuration checking. > > Suggested-by: Dan Williams <dan.j.williams@intel.com> > Signed-off-by: Dave Jiang <dave.jiang@intel.com> > --- > drivers/cxl/port.c | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) This also needs updates to: Documentation/driver-api/cxl/memory-devices.rst > > diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c > index 5453771bf330..e3e93e1b663e 100644 > --- a/drivers/cxl/port.c > +++ b/drivers/cxl/port.c > @@ -123,8 +123,30 @@ static struct attribute_group cxl_cdat_attribute_group = { > .is_bin_visible = cxl_port_bin_attr_is_visible, > }; > > +static ssize_t interleave_mask_show(struct device *dev, struct device_attribute *attr, > + char *buf) > +{ > + struct cxl_hdm *cxlhdm = dev_get_drvdata(dev); > + > + if (!cxlhdm) > + return 0; Given that this is an attribute in 'struct device_driver'.dev_groups it is guaranteed to only be visible while the device is successfully attached to its driver. So this check is not necessary. > + > + return sysfs_emit(buf, "%#x\n", cxlhdm->interleave_mask); > +} > +static DEVICE_ATTR_RO(interleave_mask); > + > +static struct attribute *cxl_port_info_attributes[] = { > + &dev_attr_interleave_mask.attr, > + NULL, > +}; > + > +static struct attribute_group cxl_port_info_attribute_group = { > + .attrs = cxl_port_info_attributes, > +}; > + > static const struct attribute_group *cxl_port_attribute_groups[] = { Lets do a lead in patch to rename this to avoid the confusion with the static port attributes in the core: s/cxl_port_attribute_groups/cxl_port_dynamic_attr_groups/
diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 5453771bf330..e3e93e1b663e 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -123,8 +123,30 @@ static struct attribute_group cxl_cdat_attribute_group = { .is_bin_visible = cxl_port_bin_attr_is_visible, }; +static ssize_t interleave_mask_show(struct device *dev, struct device_attribute *attr, + char *buf) +{ + struct cxl_hdm *cxlhdm = dev_get_drvdata(dev); + + if (!cxlhdm) + return 0; + + return sysfs_emit(buf, "%#x\n", cxlhdm->interleave_mask); +} +static DEVICE_ATTR_RO(interleave_mask); + +static struct attribute *cxl_port_info_attributes[] = { + &dev_attr_interleave_mask.attr, + NULL, +}; + +static struct attribute_group cxl_port_info_attribute_group = { + .attrs = cxl_port_info_attributes, +}; + static const struct attribute_group *cxl_port_attribute_groups[] = { &cxl_cdat_attribute_group, + &cxl_port_info_attribute_group, NULL, };
Export the interleave address mask as a sysfs attribute for a port. The interleave address mask is created based off the CXL HDM Decoder Capability Register (CXL spec v3 8.2.4.19.1) and sets the bits indicated by th "A11to8 Interleave Capable" bit and the "A14to12 Interleave Capable" bit. It indicates the decoder supports interleaveing based on those address bits. The exported sysfs attribute will help user region creation to do more valid configuration checking. Suggested-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- drivers/cxl/port.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)