| Message ID | 166077132400.1743055.3807533324287792337.stgit@djiang5-desk4.jf.intel.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add sanity check for interleave setup | expand |
On Wed, 17 Aug 2022 14:22:04 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > Export the interleave address mask as a sysfs attribute for a port. The > interleave address mask is created based off the CXL HDM Decoder Capability > Register (CXL spec v3 8.2.4.19.1) and sets the bits indicated by th "A11to8 the > Interleave Capable" bit and the "A14to12 Interleave Capable" bit. It > indicates the decoder supports interleaveing based on those address bits. interleaving (spelling from the spec.) > The exported sysfs attribute will help user region creation to do more > valid configuration checking. > > Suggested-by: Dan Williams <dan.j.williams@intel.com> > Signed-off-by: Dave Jiang <dave.jiang@intel.com> Looks good other than needing a spell check (not that I can take the high ground on spelling, or remembering to spell check patches ;) Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > Documentation/ABI/testing/sysfs-bus-cxl | 11 +++++++++++ > drivers/cxl/port.c | 19 +++++++++++++++++++ > 2 files changed, 30 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl > index 8494ef27e8d2..c6f533f47e50 100644 > --- a/Documentation/ABI/testing/sysfs-bus-cxl > +++ b/Documentation/ABI/testing/sysfs-bus-cxl > @@ -191,6 +191,17 @@ Description: > the data is 0 reading the CDAT data failed. Otherwise the CDAT > data is reported. > > +What: /sys/bus/cxl/devices/endpointX/interleave_mask > + /sys/bus/cxl/devices/portX/interleave_mask > +Date: Aug, 2020 > +KernelVersion: v6.1 > +Contact: linux-cxl@vger.kernel.org > +Description: > + (RO) Interleve address mask from the HDM decoder attached to the Interleave > + port. The address bits are set depending on the CXL HDM Decoder > + Capability Register (CXL spec v3 8.2.4.19.1) where the "A11to8 rev3.0 Technically it's version 1 of revision 3 > + Interleave Capable" bit and the "AA14to12 Interleave Capable" bits > + are set. > > What: /sys/bus/cxl/devices/decoderX.Y/mode > Date: May, 2022 > diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c > index c4aa073b7e31..567f62fd4ded 100644 > --- a/drivers/cxl/port.c > +++ b/drivers/cxl/port.c > @@ -123,8 +123,27 @@ static struct attribute_group cxl_cdat_attribute_group = { > .is_bin_visible = cxl_port_bin_attr_is_visible, > }; > > +static ssize_t interleave_mask_show(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + struct cxl_hdm *cxlhdm = dev_get_drvdata(dev); > + > + return sysfs_emit(buf, "%#x\n", cxlhdm->interleave_mask); > +} > +static DEVICE_ATTR_RO(interleave_mask); > + > +static struct attribute *cxl_port_info_attributes[] = { > + &dev_attr_interleave_mask.attr, > + NULL, I'd not put a comma after a NULL terminator, but just did a grep and this inline with rest of drivers/cxl so fair enough. > +}; > + > +static struct attribute_group cxl_port_info_attribute_group = { > + .attrs = cxl_port_info_attributes, > +}; > + > static const struct attribute_group *cxl_port_dynamic_attr_groups[] = { > &cxl_cdat_attribute_group, > + &cxl_port_info_attribute_group, > NULL, > }; > > >
diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 8494ef27e8d2..c6f533f47e50 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -191,6 +191,17 @@ Description: the data is 0 reading the CDAT data failed. Otherwise the CDAT data is reported. +What: /sys/bus/cxl/devices/endpointX/interleave_mask + /sys/bus/cxl/devices/portX/interleave_mask +Date: Aug, 2020 +KernelVersion: v6.1 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) Interleve address mask from the HDM decoder attached to the + port. The address bits are set depending on the CXL HDM Decoder + Capability Register (CXL spec v3 8.2.4.19.1) where the "A11to8 + Interleave Capable" bit and the "AA14to12 Interleave Capable" bits + are set. What: /sys/bus/cxl/devices/decoderX.Y/mode Date: May, 2022 diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index c4aa073b7e31..567f62fd4ded 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -123,8 +123,27 @@ static struct attribute_group cxl_cdat_attribute_group = { .is_bin_visible = cxl_port_bin_attr_is_visible, }; +static ssize_t interleave_mask_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_hdm *cxlhdm = dev_get_drvdata(dev); + + return sysfs_emit(buf, "%#x\n", cxlhdm->interleave_mask); +} +static DEVICE_ATTR_RO(interleave_mask); + +static struct attribute *cxl_port_info_attributes[] = { + &dev_attr_interleave_mask.attr, + NULL, +}; + +static struct attribute_group cxl_port_info_attribute_group = { + .attrs = cxl_port_info_attributes, +}; + static const struct attribute_group *cxl_port_dynamic_attr_groups[] = { &cxl_cdat_attribute_group, + &cxl_port_info_attribute_group, NULL, };
Export the interleave address mask as a sysfs attribute for a port. The interleave address mask is created based off the CXL HDM Decoder Capability Register (CXL spec v3 8.2.4.19.1) and sets the bits indicated by th "A11to8 Interleave Capable" bit and the "A14to12 Interleave Capable" bit. It indicates the decoder supports interleaveing based on those address bits. The exported sysfs attribute will help user region creation to do more valid configuration checking. Suggested-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- Documentation/ABI/testing/sysfs-bus-cxl | 11 +++++++++++ drivers/cxl/port.c | 19 +++++++++++++++++++ 2 files changed, 30 insertions(+)