| Message ID | 166144367188.745916.2815396662040037518.stgit@djiang5-desk3.ch.intel.com |
|---|---|
| State | Under Review |
| Delegated to: | Dan Williams |
| Headers | show |
| Series | Add sanity check for interleave setup | expand |
On Thu, 25 Aug 2022 09:07:51 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > Attach the cxl mock hdm to the port device to allow cxl_interleave_capable() > to check the interleave configuration. Set the interleave_mask as well > to support the new verification code. > > Reviewed-by: Dan Williams <dan.j.williams@intel.com> > Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > tools/testing/cxl/test/cxl.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c > index 4b361ed63333..85000d1b5812 100644 > --- a/tools/testing/cxl/test/cxl.c > +++ b/tools/testing/cxl/test/cxl.c > @@ -398,6 +398,8 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port) > return ERR_PTR(-ENOMEM); > > cxlhdm->port = port; > + cxlhdm->interleave_mask = GENMASK(14, 8); > + cxlhdm->interleave_cap = CXL_HDM_INTERLEAVE_CAP_BASELINE; > dev_set_drvdata(&port->dev, cxlhdm); > return cxlhdm; > } > >
diff --git a/tools/testing/cxl/test/cxl.c b/tools/testing/cxl/test/cxl.c index 4b361ed63333..85000d1b5812 100644 --- a/tools/testing/cxl/test/cxl.c +++ b/tools/testing/cxl/test/cxl.c @@ -398,6 +398,8 @@ static struct cxl_hdm *mock_cxl_setup_hdm(struct cxl_port *port) return ERR_PTR(-ENOMEM); cxlhdm->port = port; + cxlhdm->interleave_mask = GENMASK(14, 8); + cxlhdm->interleave_cap = CXL_HDM_INTERLEAVE_CAP_BASELINE; dev_set_drvdata(&port->dev, cxlhdm); return cxlhdm; }