| Message ID | 166664850753.511468.15931290944330812647.stgit@djiang5-desk3.ch.intel.com |
|---|---|
| State | New, archived |
| Headers | show |
| Series | cxl: update eiw_to_ways() comment referring to cxl spec | expand |
On Mon, 24 Oct 2022 14:55:07 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > Change comment pointing to CLX ECN to the releveant released rev3 spec. > > Suggested-by: Alison Schofield <alison.schofield@intel.com> > Signed-off-by: Dave Jiang <dave.jiang@intel.com> Confirmed reference is correct. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/cxl.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index e2a1a7523a2b..512ba28a6349 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -77,7 +77,7 @@ static inline int eig_to_granularity(u16 eig, unsigned int *granularity) > return 0; > } > > -/* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ > +/* Encode defined in CXL rev3.0 8.2.4.19.7 CXL HDM Decoder n Control Register */ > static inline int eiw_to_ways(u8 eiw, unsigned int *ways) > { > switch (eiw) { > >
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index e2a1a7523a2b..512ba28a6349 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -77,7 +77,7 @@ static inline int eig_to_granularity(u16 eig, unsigned int *granularity) return 0; } -/* Encode defined in CXL ECN "3, 6, 12 and 16-way memory Interleaving" */ +/* Encode defined in CXL rev3.0 8.2.4.19.7 CXL HDM Decoder n Control Register */ static inline int eiw_to_ways(u8 eiw, unsigned int *ways) { switch (eiw) {
Change comment pointing to CLX ECN to the releveant released rev3 spec. Suggested-by: Alison Schofield <alison.schofield@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- drivers/cxl/cxl.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)