From patchwork Thu Dec 8 21:28:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Williams X-Patchwork-Id: 13068943 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 465C9C4167B for ; Thu, 8 Dec 2022 21:28:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229675AbiLHV2m (ORCPT ); Thu, 8 Dec 2022 16:28:42 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229478AbiLHV2l (ORCPT ); Thu, 8 Dec 2022 16:28:41 -0500 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 60F488424A for ; Thu, 8 Dec 2022 13:28:40 -0800 (PST) DKIM-Signature: v=1; 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d="scan'208";a="753756119" Received: from kputnam-mobl1.amr.corp.intel.com (HELO dwillia2-xfh.jf.intel.com) ([10.251.25.149]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Dec 2022 13:28:39 -0800 Subject: [ndctl PATCH v2 07/18] cxl/list: Add parent_dport attribute to port listings From: Dan Williams To: linux-cxl@vger.kernel.org Cc: vishal.l.verma@intel.com, alison.schofield@intel.com, nvdimm@lists.linux.dev, vishal.l.verma@intel.com Date: Thu, 08 Dec 2022 13:28:39 -0800 Message-ID: <167053491908.582963.7783814693644991382.stgit@dwillia2-xfh.jf.intel.com> In-Reply-To: <167053487710.582963.17616889985000817682.stgit@dwillia2-xfh.jf.intel.com> References: <167053487710.582963.17616889985000817682.stgit@dwillia2-xfh.jf.intel.com> User-Agent: StGit/0.18-3-g996c MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org --- cxl/json.c | 8 ++++++++ cxl/lib/libcxl.c | 38 ++++++++++++++++++++++++++++++++++++++ cxl/lib/libcxl.sym | 1 + cxl/lib/private.h | 2 ++ cxl/libcxl.h | 1 + 5 files changed, 50 insertions(+) diff --git a/cxl/json.c b/cxl/json.c index 5cff532acb13..2f3639ede2f8 100644 --- a/cxl/json.c +++ b/cxl/json.c @@ -783,6 +783,14 @@ static struct json_object *__util_cxl_port_to_json(struct cxl_port *port, if (jobj) json_object_object_add(jport, "host", jobj); + if (cxl_port_get_parent_dport(port)) { + struct cxl_dport *dport = cxl_port_get_parent_dport(port); + + jobj = json_object_new_string(cxl_dport_get_devname(dport)); + if (jobj) + json_object_object_add(jport, "parent_dport", jobj); + } + jobj = json_object_new_int(cxl_port_get_depth(port)); if (jobj) json_object_object_add(jport, "depth", jobj); diff --git a/cxl/lib/libcxl.c b/cxl/lib/libcxl.c index a69e31bc8a6e..9475d0e51f8c 100644 --- a/cxl/lib/libcxl.c +++ b/cxl/lib/libcxl.c @@ -162,6 +162,7 @@ static void __free_port(struct cxl_port *port, struct list_head *head) free(port->dev_buf); free(port->dev_path); free(port->uport); + free(port->parent_dport_path); } static void free_port(struct cxl_port *port, struct list_head *head) @@ -1488,6 +1489,20 @@ static int cxl_port_init(struct cxl_port *port, struct cxl_port *parent_port, if (!port->uport) goto err; + /* + * CXL root devices have no parents and level 1 ports are both + * CXL root targets and hosts of the next level, so: + * parent_dport == uport + * ...at depth == 1 + */ + if (port->depth > 1) { + rc = snprintf(port->dev_buf, port->buf_len, "%s/parent_dport", + cxlport_base); + if (rc >= port->buf_len) + goto err; + port->parent_dport_path = realpath(port->dev_buf, NULL); + } + sprintf(path, "%s/modalias", cxlport_base); if (sysfs_read_attr(ctx, path, buf) == 0) port->module = util_modalias_to_module(ctx, buf); @@ -2465,6 +2480,29 @@ CXL_EXPORT const char *cxl_port_get_host(struct cxl_port *port) return devpath_to_devname(port->uport); } +CXL_EXPORT struct cxl_dport *cxl_port_get_parent_dport(struct cxl_port *port) +{ + struct cxl_port *parent; + struct cxl_dport *dport; + const char *name; + + if (port->parent_dport) + return port->parent_dport; + + if (!port->parent_dport_path) + return NULL; + + parent = cxl_port_get_parent(port); + name = devpath_to_devname(port->parent_dport_path); + cxl_dport_foreach(parent, dport) + if (strcmp(cxl_dport_get_devname(dport), name) == 0) { + port->parent_dport = dport; + return dport; + } + + return NULL; +} + CXL_EXPORT bool cxl_port_hosts_memdev(struct cxl_port *port, struct cxl_memdev *memdev) { diff --git a/cxl/lib/libcxl.sym b/cxl/lib/libcxl.sym index 490ed1fda5d3..cc5c1d543484 100644 --- a/cxl/lib/libcxl.sym +++ b/cxl/lib/libcxl.sym @@ -222,4 +222,5 @@ LIBCXL_4 { global: cxl_target_get_firmware_node; cxl_dport_get_firmware_node; + cxl_port_get_parent_dport; } LIBCXL_3; diff --git a/cxl/lib/private.h b/cxl/lib/private.h index e378339ec353..da2fce33cb07 100644 --- a/cxl/lib/private.h +++ b/cxl/lib/private.h @@ -62,6 +62,8 @@ struct cxl_port { size_t buf_len; char *dev_path; char *uport; + char *parent_dport_path; + struct cxl_dport *parent_dport; int ports_init; int endpoints_init; int decoders_init; diff --git a/cxl/libcxl.h b/cxl/libcxl.h index 1e0076908901..8d75330886f8 100644 --- a/cxl/libcxl.h +++ b/cxl/libcxl.h @@ -96,6 +96,7 @@ bool cxl_port_is_endpoint(struct cxl_port *port); struct cxl_endpoint *cxl_port_to_endpoint(struct cxl_port *port); struct cxl_bus *cxl_port_get_bus(struct cxl_port *port); const char *cxl_port_get_host(struct cxl_port *port); +struct cxl_dport *cxl_port_get_parent_dport(struct cxl_port *port); bool cxl_port_hosts_memdev(struct cxl_port *port, struct cxl_memdev *memdev); int cxl_port_get_nr_dports(struct cxl_port *port); int cxl_port_disable_invalidate(struct cxl_port *port);