diff mbox series

[ndctl,2/5] cxl/filter: enumerate endpoints and memdevs in an RCH

Message ID 167097753265.1189953.11519741234147002252.stgit@dwillia2-xfh.jf.intel.com
State Accepted
Commit 382765f9dc5d62b3e54219b9207be5483e61bc60
Headers show
Series cxl/test: Reliability fixes | expand

Commit Message

Dan Williams Dec. 14, 2022, 12:25 a.m. UTC 
From: Vishal Verma <vishal.l.verma@intel.com>

An RCH (Restricted CXL Host) is a platform limited to a smaller subset
of CXL functionality (formerly known as a CXL1.1 platform). Such a
playform may still be able to host a CXL device with a higher spec level
(section 9.11.8 CXL Devices Attached to an RCH in the CXL 3.0
specification).

The caveat with such a configuration is that the endpoints will appear
as 'Root Complex integrated Endpoints' (RCiEPs). In libcxl terms, the
endpoint would be connected directly to the cxl_bus object.

Until now, cxl-list and cxl_filter_walk() assume that endpoints must be
under a cxl_port, which is true for CXL VH topologies. To account for
endpoints in RCH topologies, change cxl_filter_walk() to also account
for endpoints that may appear directly under a cxl_bus object.

With this change, an example CXL RCH topology may enumerate as follows:

    # cxl list -v
    [
      {
        "bus":"root0",
        "provider":"ACPI.CXL",
        "nr_dports":1,
        "dports":[
          {
            "dport":"pci0000:38",
            "id":49
          }
        ],
        "endpoints:root0":[
          {
            "endpoint":"endpoint1",
            "host":"mem0",
            "depth":1,
            "memdev":{
              "memdev":"mem0",
              "pmem_size":0,
              "ram_size":17179869184,
              "serial":0,
              "numa_node":0,
              "host":"0000:38:00.0"
            },
            "decoders:endpoint1":[
              {
                "decoder":"decoder1.0",
                "resource":36507222016,
                "size":17179869184,
                "interleave_ways":1
              }
            ]
          }
        ]
      }
    ]

[djbw: support mixed VH + RCH topologies (cxl_test)]
Co-developed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Vishal Verma <vishal.l.verma@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
---
 cxl/filter.c |    8 ++++++++
 1 file changed, 8 insertions(+)
diff mbox series

Patch

diff --git a/cxl/filter.c b/cxl/filter.c
index 8499450ded01..90b13be79d9c 100644
--- a/cxl/filter.c
+++ b/cxl/filter.c
@@ -1168,6 +1168,14 @@  walk_children:
 		walk_decoders(port, p, pick_array(jchilddecoders, jbusdecoders),
 			      pick_array(jchildregions, jregions), flags);
 
+		dbg(p, "walk rch endpoints\n");
+		if (p->endpoints || p->memdevs || p->decoders)
+			walk_endpoints(port, p,
+				       pick_array(jchildeps, jeps),
+				       pick_array(jchilddevs, jdevs),
+				       pick_array(jchilddecoders, jepdecoders),
+				       flags);
+
 		dbg(p, "walk ports\n");
 		walk_child_ports(port, p, pick_array(jchildports, jports),
 				 pick_array(jchilddecoders, jportdecoders),