| Message ID | 168357889098.2756219.3746540473463747491.stgit@djiang5-mobl3 |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cxl: Add support for QTG ID retrieval for CXL subsystem | expand |
On Mon, 08 May 2023 13:48:10 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > Export qos_class sysfs attributes for the CXL memory device. The QoS clas > should show up as /sys/bus/cxl/devices/memX/ram/qos_class for the volatile > partition and /sys/bus/cxl/devices/memX/pmem/qos_class for the persistent > partition. The QTG ID is retrieved via _DSM after supplying the > calculated bandwidth and latency for the entire CXL path from device to > the CPU. This ID is used to match up to the root decoder QoS class to > determine which CFMWS the memory range of a hotplugged CXL mem device > should be assigned under. > > While there may be multiple DSMAS exported by the device CDAT, the driver > will only expose the first QTG ID per partition in sysfs for now. In the > future when multiple QTG IDs are necessary, they can be exposed. [1] > > [1]: https://lore.kernel.org/linux-cxl/167571650007.587790.10040913293130712882.stgit@djiang5-mobl3.local/T/#md2a47b1ead3e1ba08f50eab29a4af1aed1d215ab > > Suggested-by: Dan Williams <dan.j.williams@intel.com> > Signed-off-by: Dave Jiang <dave.jiang@intel.com> > Reading this patch made me notice the whole issue of we may be exporting a useless QTG for the device due to a missmatch of memory type and CFMWS (as not using the full list provided by the _DSM) > --- > v5: > - Change qtg_id to qos_class > v4: > - Change kernel version for documentation to v6.5 > v3: > - Expand description of qtg_id. (Alison) > --- > Documentation/ABI/testing/sysfs-bus-cxl | 32 +++++++++++++++++++++++++++++++ > drivers/cxl/core/memdev.c | 26 +++++++++++++++++++++++++ > 2 files changed, 58 insertions(+) > > diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl > index 2f24e42ef36d..c13ae49dd9aa 100644 > --- a/Documentation/ABI/testing/sysfs-bus-cxl > +++ b/Documentation/ABI/testing/sysfs-bus-cxl > @@ -28,6 +28,22 @@ Description: > Payload in the CXL-2.0 specification. > > > +What: /sys/bus/cxl/devices/memX/ram/qos_class > +Date: May, 2023 > +KernelVersion: v6.5 > +Contact: linux-cxl@vger.kernel.org > +Description: > + (RO) For CXL host platforms that support "QoS Telemmetry" > + this attribute conveys a platform specific cookie that > + identifies a QoS performance class for the volatile > + partition of the CXL mem device. This class-id can be > + compared against a similar "qos_class" published for > + a root decoder. While it is not required that the endpoints > + map their local memory-class to a matching platform class, > + mismatches are not recommended and there are platform specific > + side-effects that may result. I think this needs to be the full ordered list from the _DSM with text suggesting that a compatible CFMWS matching the earliest entry possible should be used.
diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 2f24e42ef36d..c13ae49dd9aa 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -28,6 +28,22 @@ Description: Payload in the CXL-2.0 specification. +What: /sys/bus/cxl/devices/memX/ram/qos_class +Date: May, 2023 +KernelVersion: v6.5 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) For CXL host platforms that support "QoS Telemmetry" + this attribute conveys a platform specific cookie that + identifies a QoS performance class for the volatile + partition of the CXL mem device. This class-id can be + compared against a similar "qos_class" published for + a root decoder. While it is not required that the endpoints + map their local memory-class to a matching platform class, + mismatches are not recommended and there are platform specific + side-effects that may result. + + What: /sys/bus/cxl/devices/memX/pmem/size Date: December, 2020 KernelVersion: v5.12 @@ -38,6 +54,22 @@ Description: Payload in the CXL-2.0 specification. +What: /sys/bus/cxl/devices/memX/pmem/qos_class +Date: May, 2023 +KernelVersion: v6.5 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) For CXL host platforms that support "QoS Telemmetry" + this attribute conveys a platform specific cookie that + identifies a QoS performance class for the persistent + partition of the CXL mem device. This class-id can be + compared against a similar "qos_class" published for + a root decoder. While it is not required that the endpoints + map their local memory-class to a matching platform class, + mismatches are not recommended and there are platform specific + side-effects that may result. + + What: /sys/bus/cxl/devices/memX/serial Date: January, 2022 KernelVersion: v5.18 diff --git a/drivers/cxl/core/memdev.c b/drivers/cxl/core/memdev.c index 28a05f2fe32d..8e183bef33e8 100644 --- a/drivers/cxl/core/memdev.c +++ b/drivers/cxl/core/memdev.c @@ -76,6 +76,18 @@ static ssize_t ram_size_show(struct device *dev, struct device_attribute *attr, static struct device_attribute dev_attr_ram_size = __ATTR(size, 0444, ram_size_show, NULL); +static ssize_t ram_qos_class_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + + return sysfs_emit(buf, "%d\n", cxlds->ram_qos_class); +} + +static struct device_attribute dev_attr_ram_qos_class = + __ATTR(qos_class, 0444, ram_qos_class_show, NULL); + static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -89,6 +101,18 @@ static ssize_t pmem_size_show(struct device *dev, struct device_attribute *attr, static struct device_attribute dev_attr_pmem_size = __ATTR(size, 0444, pmem_size_show, NULL); +static ssize_t pmem_qos_class_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); + struct cxl_dev_state *cxlds = cxlmd->cxlds; + + return sysfs_emit(buf, "%d\n", cxlds->pmem_qos_class); +} + +static struct device_attribute dev_attr_pmem_qos_class = + __ATTR(qos_class, 0444, pmem_qos_class_show, NULL); + static ssize_t serial_show(struct device *dev, struct device_attribute *attr, char *buf) { @@ -117,11 +141,13 @@ static struct attribute *cxl_memdev_attributes[] = { static struct attribute *cxl_memdev_pmem_attributes[] = { &dev_attr_pmem_size.attr, + &dev_attr_pmem_qos_class.attr, NULL, }; static struct attribute *cxl_memdev_ram_attributes[] = { &dev_attr_ram_size.attr, + &dev_attr_ram_qos_class.attr, NULL, };
Export qos_class sysfs attributes for the CXL memory device. The QoS clas should show up as /sys/bus/cxl/devices/memX/ram/qos_class for the volatile partition and /sys/bus/cxl/devices/memX/pmem/qos_class for the persistent partition. The QTG ID is retrieved via _DSM after supplying the calculated bandwidth and latency for the entire CXL path from device to the CPU. This ID is used to match up to the root decoder QoS class to determine which CFMWS the memory range of a hotplugged CXL mem device should be assigned under. While there may be multiple DSMAS exported by the device CDAT, the driver will only expose the first QTG ID per partition in sysfs for now. In the future when multiple QTG IDs are necessary, they can be exposed. [1] [1]: https://lore.kernel.org/linux-cxl/167571650007.587790.10040913293130712882.stgit@djiang5-mobl3.local/T/#md2a47b1ead3e1ba08f50eab29a4af1aed1d215ab Suggested-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> --- v5: - Change qtg_id to qos_class v4: - Change kernel version for documentation to v6.5 v3: - Expand description of qtg_id. (Alison) --- Documentation/ABI/testing/sysfs-bus-cxl | 32 +++++++++++++++++++++++++++++++ drivers/cxl/core/memdev.c | 26 +++++++++++++++++++++++++ 2 files changed, 58 insertions(+)