| Message ID | 168679263124.3436160.6228910132469454346.stgit@dwillia2-xfh.jf.intel.com |
|---|---|
| State | Accepted |
| Commit | f3c8a37a432e65dda1384929198dd12c1df3ea38 |
| Headers | show |
| Series | Device memory prep | expand |
On 6/14/23 18:30, Dan Williams wrote: > The current check for 256B Flit mode is incomplete and unnecessary. It > is incomplete because it fails to consider the link speed, or check for > CXL link capabilities. It is unnecessary because unconditionally > unmasking 256B Flit errors is a nop when 256B Flit operation is not > available. > > Remove this check in preparation for creating a cxl_probe_link() helper > to centralize this detection. > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> > --- > drivers/cxl/pci.c | 18 ++---------------- > 1 file changed, 2 insertions(+), 16 deletions(-) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index 4e2845b7331a..3f78082014cc 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -368,19 +368,6 @@ static bool is_cxl_restricted(struct pci_dev *pdev) > return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; > } > > -/* > - * CXL v3.0 6.2.3 Table 6-4 > - * The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits > - * mode, otherwise it's 68B flits mode. > - */ > -static bool cxl_pci_flit_256(struct pci_dev *pdev) > -{ > - u16 lnksta2; > - > - pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &lnksta2); > - return lnksta2 & PCI_EXP_LNKSTA2_FLIT; > -} > - > static int cxl_pci_ras_unmask(struct pci_dev *pdev) > { > struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); > @@ -407,9 +394,8 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) > addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET; > orig_val = readl(addr); > > - mask = CXL_RAS_UNCORRECTABLE_MASK_MASK; > - if (!cxl_pci_flit_256(pdev)) > - mask &= ~CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; > + mask = CXL_RAS_UNCORRECTABLE_MASK_MASK | > + CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; > val = orig_val & ~mask; > writel(val, addr); > dev_dbg(&pdev->dev, >
On Thu, 15 Jun 2023 14:34:00 -0700 Dave Jiang <dave.jiang@intel.com> wrote: > On 6/14/23 18:30, Dan Williams wrote: > > The current check for 256B Flit mode is incomplete and unnecessary. It > > is incomplete because it fails to consider the link speed, or check for > > CXL link capabilities. It is unnecessary because unconditionally > > unmasking 256B Flit errors is a nop when 256B Flit operation is not > > available. > > > > Remove this check in preparation for creating a cxl_probe_link() helper > > to centralize this detection. > > > > Signed-off-by: Dan Williams <dan.j.williams@intel.com> > > Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 4e2845b7331a..3f78082014cc 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -368,19 +368,6 @@ static bool is_cxl_restricted(struct pci_dev *pdev) return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; } -/* - * CXL v3.0 6.2.3 Table 6-4 - * The table indicates that if PCIe Flit Mode is set, then CXL is in 256B flits - * mode, otherwise it's 68B flits mode. - */ -static bool cxl_pci_flit_256(struct pci_dev *pdev) -{ - u16 lnksta2; - - pcie_capability_read_word(pdev, PCI_EXP_LNKSTA2, &lnksta2); - return lnksta2 & PCI_EXP_LNKSTA2_FLIT; -} - static int cxl_pci_ras_unmask(struct pci_dev *pdev) { struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); @@ -407,9 +394,8 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_MASK_OFFSET; orig_val = readl(addr); - mask = CXL_RAS_UNCORRECTABLE_MASK_MASK; - if (!cxl_pci_flit_256(pdev)) - mask &= ~CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; + mask = CXL_RAS_UNCORRECTABLE_MASK_MASK | + CXL_RAS_UNCORRECTABLE_MASK_F256B_MASK; val = orig_val & ~mask; writel(val, addr); dev_dbg(&pdev->dev,
The current check for 256B Flit mode is incomplete and unnecessary. It is incomplete because it fails to consider the link speed, or check for CXL link capabilities. It is unnecessary because unconditionally unmasking 256B Flit errors is a nop when 256B Flit operation is not available. Remove this check in preparation for creating a cxl_probe_link() helper to centralize this detection. Signed-off-by: Dan Williams <dan.j.williams@intel.com> --- drivers/cxl/pci.c | 18 ++---------------- 1 file changed, 2 insertions(+), 16 deletions(-)