@@ -557,8 +557,21 @@ static int cxl_get_chbcr(union acpi_subtable_headers *header, void *arg,
return 0;
}
+static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)
+{
+ struct acpi_device *hb = to_cxl_host_bridge(NULL, dev);
+ u8 handle[ACPI_SRAT_DEVICE_HANDLE_SIZE] = { 0 };
+
+ /* ACPI spec 6.5 table 5.65 */
+ strncpy(handle, acpi_device_hid(hb), 8);
+ strncpy(&handle[8], acpi_device_uid(hb), 4);
+
+ return acpi_get_genport_coordinates(handle, &dport->hb_access);
+}
+
static int add_host_bridge_dport(struct device *match, void *arg)
{
+ int ret;
acpi_status rc;
struct device *bridge;
unsigned long long uid;
@@ -614,6 +627,10 @@ static int add_host_bridge_dport(struct device *match, void *arg)
if (IS_ERR(dport))
return PTR_ERR(dport);
+ ret = get_genport_coordinates(match, dport);
+ if (ret)
+ dev_dbg(match, "Failed to get generic port perf coordinates.\n");
+
return 0;
}
@@ -636,6 +636,7 @@ cxl_find_dport_by_dev(struct cxl_port *port, const struct device *dport_dev)
* @rcrb: base address for the Root Complex Register Block
* @rch: Indicate whether this dport was enumerated in RCH or VH mode
* @port: reference to cxl_port that contains this downstream port
+ * @genport_coord: access coordinates (performance) from ACPI generic port
* @coord: access coordinates (performance) for switch from CDAT
* @link_latency: calculated PCIe downstream latency
*/
@@ -646,6 +647,7 @@ struct cxl_dport {
resource_size_t rcrb;
bool rch;
struct cxl_port *port;
+ struct access_coordinate hb_access;
struct access_coordinate coord;
long link_latency;
};