| Message ID | 20210520184138.996337-1-ben.widawsky@intel.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v2] cxl: Rename mem to pci | expand |
On Thu, May 20, 2021 at 11:41 AM Ben Widawsky <ben.widawsky@intel.com> wrote: > > As the driver has undergone development, it's become clear that the > majority [entirety?] of the current functionality in mem.c is actually a > layer encapsulating functionality exposed through PCI based > interactions. This layer can be used either in isolation or to provide > functionality for higher level functionality. > > CXL capabilities exist in a parallel domain to PCIe. CXL devices are > enumerable and controllable via "legacy" PCIe mechanisms; however, their > CXL capabilities are a superset of PCIe. For example, a CXL device may > be connected to a non-CXL capable PCIe root port, and therefore will not > be able to participate in CXL.mem or CXL.cache operations, but can still > be accessed through PCIe mechanisms for CXL.io operations. > > To properly represent the PCI nature of this driver, and in preparation for > introducing a new driver for the CXL.mem / HDM decoder (Host-managed Device > Memory) capabilities of a CXL memory expander, rename mem.c to pci.c so that > mem.c is available for this new driver. > > The result of the change is that there is a clear layering distinction > in the driver, and a systems administrator may load only the cxl_pci > module and gain access to such operations as, firmware update, offline > provisioning of devices, and error collection. In addition to freeing up > the file name for another purpose, there are two primary reasons this is > useful, > 1. Acting upon devices which don't have full CXL capabilities. This > may happen for instance if the CXL device is connected in a CXL > unaware part of the platform topology. > 2. Userspace-first provisioning for devices without kernel driver > interference. This may be useful when provisioning a new device > in a specific manner that might otherwise be blocked or prevented > by the real CXL mem driver. > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > --- > v2: Makes it clear that the main motivation for this patch is for proper > layering and that administrative PCI-only activities is a secondary benefit. > > I'm proposing we take the hit now and merge this as our next patch for cxl/next. Looks good to me, and I think low risk to expedite into cxl/next to remove the burden on git to cope with other development touching these files. Reviewed-by: Dan Williams <dan.j.williams@intel.com>
diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst index 71495ed77069..a927169db984 100644 --- a/Documentation/driver-api/cxl/memory-devices.rst +++ b/Documentation/driver-api/cxl/memory-devices.rst @@ -22,10 +22,10 @@ This section covers the driver infrastructure for a CXL memory device. CXL Memory Device ----------------- -.. kernel-doc:: drivers/cxl/mem.c - :doc: cxl mem +.. kernel-doc:: drivers/cxl/pci.c + :doc: cxl pci -.. kernel-doc:: drivers/cxl/mem.c +.. kernel-doc:: drivers/cxl/pci.c :internal: CXL Core diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index 97dc4d751651..5483ba92b6da 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -21,15 +21,10 @@ config CXL_MEM as if the memory was attached to the typical CPU memory controller. - Say 'y/m' to enable a driver (named "cxl_mem.ko" when built as - a module) that will attach to CXL.mem devices for - configuration, provisioning, and health monitoring. This - driver is required for dynamic provisioning of CXL.mem - attached memory which is a prerequisite for persistent memory - support. Typically volatile memory is mapped by platform - firmware and included in the platform memory map, but in some - cases the OS is responsible for mapping that memory. See - Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification. + Say 'y/m' to enable a driver that will attach to CXL.mem devices for + configuration and management primarily via the mailbox interface. See + Chapter 2.3 Type 3 CXL Device in the CXL 2.0 specification for more + details. If unsure say 'm'. diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index 3808e39dd31f..10b204025d3b 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CXL_BUS) += cxl_core.o -obj-$(CONFIG_CXL_MEM) += cxl_mem.o +obj-$(CONFIG_CXL_MEM) += cxl_pci.o ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL cxl_core-y := core.o -cxl_mem-y := mem.o +cxl_pci-y := pci.o +cxl_acpi-y := acpi.o diff --git a/drivers/cxl/mem.c b/drivers/cxl/pci.c similarity index 99% rename from drivers/cxl/mem.c rename to drivers/cxl/pci.c index c5fdf2c57181..c7996c2a2054 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/pci.c @@ -16,10 +16,11 @@ #include "mem.h" /** - * DOC: cxl mem + * DOC: cxl pci * - * This implements a CXL memory device ("type-3") as it is defined by the - * Compute Express Link specification. + * This implements the PCI exclusive functionality for a CXL device as it is + * defined by the Compute Express Link specification. CXL devices may surface + * certain functionality even if it isn't CXL enabled. * * The driver has several responsibilities, mainly: * - Create the memX device and register on the CXL bus. @@ -27,8 +28,6 @@ * - Probe the device attributes to establish sysfs interface. * - Provide an IOCTL interface to userspace to communicate with the device for * things like firmware update. - * - Support management of interleave sets. - * - Handle and manage error conditions. */ #define cxl_doorbell_busy(cxlm) \
As the driver has undergone development, it's become clear that the majority [entirety?] of the current functionality in mem.c is actually a layer encapsulating functionality exposed through PCI based interactions. This layer can be used either in isolation or to provide functionality for higher level functionality. CXL capabilities exist in a parallel domain to PCIe. CXL devices are enumerable and controllable via "legacy" PCIe mechanisms; however, their CXL capabilities are a superset of PCIe. For example, a CXL device may be connected to a non-CXL capable PCIe root port, and therefore will not be able to participate in CXL.mem or CXL.cache operations, but can still be accessed through PCIe mechanisms for CXL.io operations. To properly represent the PCI nature of this driver, and in preparation for introducing a new driver for the CXL.mem / HDM decoder (Host-managed Device Memory) capabilities of a CXL memory expander, rename mem.c to pci.c so that mem.c is available for this new driver. The result of the change is that there is a clear layering distinction in the driver, and a systems administrator may load only the cxl_pci module and gain access to such operations as, firmware update, offline provisioning of devices, and error collection. In addition to freeing up the file name for another purpose, there are two primary reasons this is useful, 1. Acting upon devices which don't have full CXL capabilities. This may happen for instance if the CXL device is connected in a CXL unaware part of the platform topology. 2. Userspace-first provisioning for devices without kernel driver interference. This may be useful when provisioning a new device in a specific manner that might otherwise be blocked or prevented by the real CXL mem driver. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- v2: Makes it clear that the main motivation for this patch is for proper layering and that administrative PCI-only activities is a secondary benefit. I'm proposing we take the hit now and merge this as our next patch for cxl/next. --- Documentation/driver-api/cxl/memory-devices.rst | 6 +++--- drivers/cxl/Kconfig | 13 ++++--------- drivers/cxl/Makefile | 5 +++-- drivers/cxl/{mem.c => pci.c} | 9 ++++----- 4 files changed, 14 insertions(+), 19 deletions(-) rename drivers/cxl/{mem.c => pci.c} (99%)