| Message ID | 20210715194125.898305-3-ben.widawsky@intel.com |
|---|---|
| State | New, archived |
| Headers | show |
| Series | CXL core reorganization | expand |
On Thu, Jul 15, 2021 at 12:41 PM Ben Widawsky <ben.widawsky@intel.com> wrote: > > Now that CXL core's role is well understood, the documentation should > reflect that information. Looks good to me. Reviewed-by: Dan Williams <dan.j.williams@intel.com> > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > --- > drivers/cxl/core/bus.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c > index 00b759ff92d3..f50872e8e7af 100644 > --- a/drivers/cxl/core/bus.c > +++ b/drivers/cxl/core/bus.c > @@ -12,8 +12,15 @@ > /** > * DOC: cxl core > * > - * The CXL core provides a sysfs hierarchy for control devices and a rendezvous > - * point for cross-device interleave coordination through cxl ports. > + * The CXL core provides a set of interfaces that can be consumed by CXL aware > + * drivers. The interfaces allow for creation, modification, and destruction of > + * regions, memory devices, ports, and decoders. CXL aware drivers must register > + * with the CXL core via these interfaces in order to be able to participate in > + * cross-device interleave coordination. The CXL core also establishes and > + * maintains the bridge to the nvdimm subsystem. > + * > + * CXL core introduces sysfs hierarchy to control the devices that are > + * instantiated by the core. > */ > > static DEFINE_IDA(cxl_port_ida); > -- > 2.32.0 >
diff --git a/drivers/cxl/core/bus.c b/drivers/cxl/core/bus.c index 00b759ff92d3..f50872e8e7af 100644 --- a/drivers/cxl/core/bus.c +++ b/drivers/cxl/core/bus.c @@ -12,8 +12,15 @@ /** * DOC: cxl core * - * The CXL core provides a sysfs hierarchy for control devices and a rendezvous - * point for cross-device interleave coordination through cxl ports. + * The CXL core provides a set of interfaces that can be consumed by CXL aware + * drivers. The interfaces allow for creation, modification, and destruction of + * regions, memory devices, ports, and decoders. CXL aware drivers must register + * with the CXL core via these interfaces in order to be able to participate in + * cross-device interleave coordination. The CXL core also establishes and + * maintains the bridge to the nvdimm subsystem. + * + * CXL core introduces sysfs hierarchy to control the devices that are + * instantiated by the core. */ static DEFINE_IDA(cxl_port_ida);
Now that CXL core's role is well understood, the documentation should reflect that information. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- drivers/cxl/core/bus.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)