[01/23] cxl: Move cxl_core to new directory

Message ID	20210723210623.114073-2-ben.widawsky@intel.com
State	New, archived
Headers	show Return-Path: <linux-cxl-owner@kernel.org> From: Ben Widawsky <ben.widawsky@intel.com> To: linux-cxl@vger.kernel.org Cc: Ben Widawsky <ben.widawsky@intel.com>, Alison Schofield <alison.schofield@intel.com>, Dan Williams <dan.j.williams@intel.com>, Ira Weiny <ira.weiny@intel.com>, Jonathan Cameron <Jonathan.Cameron@Huawei.com>, Vishal Verma <vishal.l.verma@intel.com> Subject: [PATCH 01/23] cxl: Move cxl_core to new directory Date: Fri, 23 Jul 2021 14:06:01 -0700 Message-Id: <20210723210623.114073-2-ben.widawsky@intel.com> In-Reply-To: <20210723210623.114073-1-ben.widawsky@intel.com> References: <20210723210623.114073-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	cxl_region and cxl_memdev drivers \| expand [RFCish,00/23] cxl_region and cxl_memdev drivers [01/23] cxl: Move cxl_core to new directory [02/23] cxl/core: Improve CXL core kernel docs [03/23] cxl/core: Extract register and pmem functionality [04/23] cxl/mem: Move character device region creation [05/23] cxl: Pass fops and shutdown to memdev creation [06/23] cxl/core: Move memdev management to core [07/23] cxl/pci: Ignore unknown register block types [08/23] cxl/pci: Simplify register setup [09/23] cxl/pci: Retain map information in cxl_mem_probe [10/23] cxl/decoder: Support parentless decoders [11/23] cxl: Enable an endpoint decoder type [12/23] cxl/region: Add region creation ABI [13/23] cxl/region: Introduce concept of region configuration [14/23] cxl: Convert driver id to an enum [15/23] cxl/region: Introduce a cxl_region driver [16/23] cxl/core: Convert decoder range to resource [17/23] cxl/region: Handle region's address space allocation [18/23] cxl/region: Only allow CXL capable targets [19/23] cxl/mem: Introduce CXL mem driver [20/23] cxl/memdev: Determine CXL.mem capability [21/23] cxl/mem: Check that the device is CXL.mem capable [22/23] cxl/mem: Add device as a port [23/23] cxl/core: Map component registers for ports

Message ID

20210723210623.114073-2-ben.widawsky@intel.com

State

New, archived

Headers

From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: Ben Widawsky <ben.widawsky@intel.com>,
        Alison Schofield <alison.schofield@intel.com>,
        Dan Williams <dan.j.williams@intel.com>,
        Ira Weiny <ira.weiny@intel.com>,
        Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
        Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 01/23] cxl: Move cxl_core to new directory
Date: Fri, 23 Jul 2021 14:06:01 -0700
Message-Id: <20210723210623.114073-2-ben.widawsky@intel.com>
In-Reply-To: <20210723210623.114073-1-ben.widawsky@intel.com>
References: <20210723210623.114073-1-ben.widawsky@intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

cxl_region and cxl_memdev drivers | expand

Commit Message

Ben Widawsky July 23, 2021, 9:06 p.m. UTC

CXL core is growing, and it's already arguably unmanageable. To support
future growth, move core functionality to a new directory and rename the
file to represent just bus support. Future work will remove non-bus
functionality.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
---
 Documentation/driver-api/cxl/memory-devices.rst | 2 +-
 drivers/cxl/Makefile                            | 4 +---
 drivers/cxl/core/Makefile                       | 5 +++++
 drivers/cxl/{core.c => core/bus.c}              | 4 ++--
 4 files changed, 9 insertions(+), 6 deletions(-)
 create mode 100644 drivers/cxl/core/Makefile
 rename drivers/cxl/{core.c => core/bus.c} (99%)

diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst
index 487ce4f41d77..a86e2c7c551a 100644
--- a/Documentation/driver-api/cxl/memory-devices.rst
+++ b/Documentation/driver-api/cxl/memory-devices.rst
@@ -36,7 +36,7 @@  CXL Core
 .. kernel-doc:: drivers/cxl/cxl.h
    :internal:
 
-.. kernel-doc:: drivers/cxl/core.c
+.. kernel-doc:: drivers/cxl/core/bus.c
    :doc: cxl core
 
 External Interfaces
diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile
index 32954059b37b..d1aaabc940f3 100644
--- a/drivers/cxl/Makefile
+++ b/drivers/cxl/Makefile
@@ -1,11 +1,9 @@ 
 # SPDX-License-Identifier: GPL-2.0
-obj-$(CONFIG_CXL_BUS) += cxl_core.o
+obj-$(CONFIG_CXL_BUS) += core/
 obj-$(CONFIG_CXL_MEM) += cxl_pci.o
 obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o
 obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o
 
-ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL
-cxl_core-y := core.o
 cxl_pci-y := pci.o
 cxl_acpi-y := acpi.o
 cxl_pmem-y := pmem.o
diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile
new file mode 100644
index 000000000000..c65e9f61abe9
--- /dev/null
+++ b/drivers/cxl/core/Makefile
@@ -0,0 +1,5 @@ 
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CXL_BUS) += cxl_core.o
+
+ccflags-y += -DDEFAULT_SYMBOL_NAMESPACE=CXL -I./drivers/cxl
+cxl_core-y := bus.o
diff --git a/drivers/cxl/core.c b/drivers/cxl/core/bus.c
similarity index 99%
rename from drivers/cxl/core.c
rename to drivers/cxl/core/bus.c
index a2e4d54fc7bc..6ce04e3976d2 100644
--- a/drivers/cxl/core.c
+++ b/drivers/cxl/core/bus.c
@@ -6,8 +6,8 @@ 
 #include <linux/pci.h>
 #include <linux/slab.h>
 #include <linux/idr.h>
-#include "cxl.h"
-#include "mem.h"
+#include <cxl.h>
+#include <mem.h>
 
 /**
  * DOC: cxl core

[01/23] cxl: Move cxl_core to new directory

Commit Message

Patch