@@ -716,6 +716,30 @@ struct cxl_decoder *devm_cxl_add_endpoint_decoder(struct device *host,
}
EXPORT_SYMBOL_GPL(devm_cxl_add_endpoint_decoder);
+int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec)
+{
+ int pos;
+
+ pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DVSEC);
+ if (!pos)
+ return 0;
+
+ while (pos) {
+ u16 vendor, id;
+
+ pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER1, &vendor);
+ pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER2, &id);
+ if (vendor == PCI_DVSEC_VENDOR_ID_CXL && dvsec == id)
+ return pos;
+
+ pos = pci_find_next_ext_capability(pdev, pos,
+ PCI_EXT_CAP_ID_DVSEC);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(cxl_mem_dvsec);
+
/**
* __cxl_driver_register - register a driver for the cxl bus
* @cxl_drv: cxl driver structure to attach
@@ -6,6 +6,7 @@
#include <cxl.h>
#include <mem.h>
+#include <pci.h>
#include <region.h>
extern const struct device_type cxl_nvdimm_bridge_type;
@@ -4,6 +4,7 @@
#include <linux/module.h>
#include <linux/pci.h>
#include "mem.h"
+#include "pci.h"
/**
* DOC: cxl mem
@@ -33,13 +34,30 @@ static int cxl_memdev_probe(struct device *dev)
{
struct cxl_memdev *cxlmd = to_cxl_memdev(dev);
struct cxl_mem *cxlm = cxlmd->cxlm;
+ struct pci_dev *pdev = cxlm->pdev;
struct device *pdev_parent = cxlm->pdev->dev.parent;
struct device *port_dev;
+ int pcie_dvsec;
+ u16 dvsec_ctrl;
port_dev = bus_find_device(&cxl_bus_type, NULL, pdev_parent, port_match);
if (!port_dev)
return -ENODEV;
+ pcie_dvsec = cxl_mem_dvsec(pdev, PCI_DVSEC_ID_PCIE_DVSEC_CXL_DVSEC_ID);
+ if (!pcie_dvsec) {
+ dev_err(dev, "Unable to determine CXL protocol support");
+ return -ENODEV;
+ }
+
+ pci_read_config_word(pdev,
+ pcie_dvsec + PCI_DVSEC_ID_CXL_PCIE_CTRL_OFFSET,
+ &dvsec_ctrl);
+ if (!(dvsec_ctrl & CXL_PCIE_MEM_ENABLE)) {
+ dev_err(dev, "CXL.cache protocol not supported on device");
+ return -ENODEV;
+ }
+
return 0;
}
@@ -971,29 +971,6 @@ static void cxl_mem_unmap_regblock(struct cxl_mem *cxlm, void __iomem *base)
pci_iounmap(cxlm->pdev, base);
}
-static int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec)
-{
- int pos;
-
- pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DVSEC);
- if (!pos)
- return 0;
-
- while (pos) {
- u16 vendor, id;
-
- pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER1, &vendor);
- pci_read_config_word(pdev, pos + PCI_DVSEC_HEADER2, &id);
- if (vendor == PCI_DVSEC_VENDOR_ID_CXL && dvsec == id)
- return pos;
-
- pos = pci_find_next_ext_capability(pdev, pos,
- PCI_EXT_CAP_ID_DVSEC);
- }
-
- return 0;
-}
-
static int cxl_probe_regs(struct cxl_mem *cxlm, void __iomem *base,
struct cxl_register_map *map)
{
@@ -11,7 +11,10 @@
*/
#define PCI_DVSEC_HEADER1_LENGTH_MASK GENMASK(31, 20)
#define PCI_DVSEC_VENDOR_ID_CXL 0x1E98
-#define PCI_DVSEC_ID_CXL 0x0
+
+#define PCI_DVSEC_ID_PCIE_DVSEC_CXL_DVSEC_ID 0x0
+#define PCI_DVSEC_ID_CXL_PCIE_CTRL_OFFSET 0xC
+#define CXL_PCIE_MEM_ENABLE BIT(2)
#define PCI_DVSEC_ID_CXL_REGLOC_DVSEC_ID 0x8
#define PCI_DVSEC_ID_CXL_REGLOC_BLOCK1_OFFSET 0xC
@@ -29,4 +32,6 @@
#define CXL_REGLOC_ADDR_MASK GENMASK(31, 16)
+int cxl_mem_dvsec(struct pci_dev *pdev, int dvsec);
+
#endif /* __CXL_PCI_H__ */
CXL.mem capability is required to participate in an interleave set. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- drivers/cxl/core/bus.c | 24 ++++++++++++++++++++++++ drivers/cxl/core/core.h | 1 + drivers/cxl/mem.c | 18 ++++++++++++++++++ drivers/cxl/pci.c | 23 ----------------------- drivers/cxl/pci.h | 7 ++++++- 5 files changed, 49 insertions(+), 24 deletions(-)