From patchwork Thu Sep 23 17:26:43 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12513427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5F8D8C433EF for ; Thu, 23 Sep 2021 17:26:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 40A5761263 for ; Thu, 23 Sep 2021 17:26:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242549AbhIWR21 (ORCPT ); Thu, 23 Sep 2021 13:28:27 -0400 Received: from mga02.intel.com ([134.134.136.20]:47623 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242543AbhIWR21 (ORCPT ); Thu, 23 Sep 2021 13:28:27 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10116"; a="211144814" X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="211144814" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2021 10:26:55 -0700 X-IronPort-AV: E=Sophos;i="5.85,316,1624345200"; d="scan'208";a="704832548" Received: from unknown (HELO bad-guy.kumite) ([10.252.132.140]) by fmsmga005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2021 10:26:54 -0700 From: Ben Widawsky To: linux-cxl@vger.kernel.org Cc: Ben Widawsky , Andrew Donnellan , Bjorn Helgaas , "David E. Box" , David Woodhouse , Frederic Barrat , Kan Liang , Lu Baolu , iommu@lists.linux-foundation.org, linux-pci@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v2 5/9] cxl/pci: Make more use of cxl_register_map Date: Thu, 23 Sep 2021 10:26:43 -0700 Message-Id: <20210923172647.72738-6-ben.widawsky@intel.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923172647.72738-1-ben.widawsky@intel.com> References: <20210923172647.72738-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The structure exists to pass around information about register mapping. Using it more extensively cleans up many existing functions. Signed-off-by: Ben Widawsky --- drivers/cxl/cxl.h | 1 + drivers/cxl/pci.c | 36 +++++++++++++++++------------------- 2 files changed, 18 insertions(+), 19 deletions(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 7d6b011dd963..3b128ce71564 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -140,6 +140,7 @@ struct cxl_device_reg_map { }; struct cxl_register_map { + void __iomem *base; u64 block_offset; u8 reg_type; u8 barno; diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bbbacbc94fbf..5eaf2736f779 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -306,35 +306,36 @@ static int cxl_pci_setup_mailbox(struct cxl_mem *cxlm) return 0; } -static void __iomem *cxl_pci_map_regblock(struct cxl_mem *cxlm, - u8 bar, u64 offset) +static int cxl_pci_map_regblock(struct cxl_mem *cxlm, struct cxl_register_map *map) { - void __iomem *addr; + int bar = map->barno; struct device *dev = cxlm->dev; struct pci_dev *pdev = to_pci_dev(dev); + resource_size_t offset = map->block_offset; /* Basic sanity check that BAR is big enough */ if (pci_resource_len(pdev, bar) < offset) { dev_err(dev, "BAR%d: %pr: too small (offset: %#llx)\n", bar, &pdev->resource[bar], (unsigned long long)offset); - return IOMEM_ERR_PTR(-ENXIO); + return -ENXIO; } - addr = pci_iomap(pdev, bar, 0); - if (!addr) { + map->base = pci_iomap(pdev, bar, 0); + if (!map->base) { dev_err(dev, "failed to map registers\n"); - return addr; + return PTR_ERR(map->base); } dev_dbg(dev, "Mapped CXL Memory Device resource bar %u @ %#llx\n", bar, offset); - return addr; + return 0; } -static void cxl_pci_unmap_regblock(struct cxl_mem *cxlm, void __iomem *base) +static void cxl_pci_unmap_regblock(struct cxl_mem *cxlm, struct cxl_register_map *map) { - pci_iounmap(to_pci_dev(cxlm->dev), base); + pci_iounmap(to_pci_dev(cxlm->dev), map->base); + map->base = 0; } static int cxl_pci_dvsec(struct pci_dev *pdev, int dvsec) @@ -360,9 +361,9 @@ static int cxl_pci_dvsec(struct pci_dev *pdev, int dvsec) return 0; } -static int cxl_probe_regs(struct cxl_mem *cxlm, void __iomem *base, - struct cxl_register_map *map) +static int cxl_probe_regs(struct cxl_mem *cxlm, struct cxl_register_map *map) { + void __iomem *base = map->base + map->block_offset; struct cxl_component_reg_map *comp_map; struct cxl_device_reg_map *dev_map; struct device *dev = cxlm->dev; @@ -487,7 +488,6 @@ static int cxl_pci_setup_regs(struct cxl_mem *cxlm) for (i = 0; i < ARRAY_SIZE(types); i++) { struct cxl_register_map map; - void __iomem *base; rc = find_register_block(pdev, types[i], &map); if (rc) { @@ -498,14 +498,12 @@ static int cxl_pci_setup_regs(struct cxl_mem *cxlm) break; } - base = cxl_pci_map_regblock(cxlm, map.barno, map.block_offset); - if (!base) { - rc = -ENOMEM; + rc = cxl_pci_map_regblock(cxlm, &map); + if (rc) break; - } - rc = cxl_probe_regs(cxlm, base + map.block_offset, &map); - cxl_pci_unmap_regblock(cxlm, base); + rc = cxl_probe_regs(cxlm, &map); + cxl_pci_unmap_regblock(cxlm, &map); if (rc) break;