From patchwork Sat Oct 16 05:15:05 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 12563181 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CA95C433FE for ; Sat, 16 Oct 2021 05:15:39 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6943960D42 for ; Sat, 16 Oct 2021 05:15:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233313AbhJPFRq (ORCPT ); Sat, 16 Oct 2021 01:17:46 -0400 Received: from mga11.intel.com ([192.55.52.93]:1732 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231582AbhJPFRp (ORCPT ); Sat, 16 Oct 2021 01:17:45 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10138"; a="225489589" X-IronPort-AV: E=Sophos;i="5.85,377,1624345200"; d="scan'208";a="225489589" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2021 22:15:37 -0700 X-IronPort-AV: E=Sophos;i="5.85,377,1624345200"; d="scan'208";a="442743226" Received: from asimon-mobl1.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.133.4]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2021 22:15:37 -0700 From: Ben Widawsky To: linux-cxl@vger.kernel.org, Chet Douglas Cc: Ben Widawsky , Dan Williams , Alison Schofield , Ira Weiny , Jonathan Cameron , Vishal Verma Subject: [RFC PATCH 01/27] cxl: Rename CXL_MEM to CXL_PCI Date: Fri, 15 Oct 2021 22:15:05 -0700 Message-Id: <20211016051531.622613-2-ben.widawsky@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211016051531.622613-1-ben.widawsky@intel.com> References: <20211016051531.622613-1-ben.widawsky@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org With the upcoming introduction of a driver to control the non-PCI aspects of CXL.mem, such as interleave set creation and configuration, there will be an opportunity to disconnection control over CXL device memory and CXL device manageability. CXL device manageability is implemented by the cxl_pci driver. Doing this rename allows the CXL memory driver to be enabled by a new config option independently of CXL device manageability through CXL.io/PCI mechanisms. Suggested-by: Dan Williams Signed-off-by: Ben Widawsky --- drivers/cxl/Kconfig | 13 ++++++------- drivers/cxl/Makefile | 2 +- 2 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/cxl/Kconfig b/drivers/cxl/Kconfig index e6de221cc568..23773d0ac896 100644 --- a/drivers/cxl/Kconfig +++ b/drivers/cxl/Kconfig @@ -13,14 +13,13 @@ menuconfig CXL_BUS if CXL_BUS -config CXL_MEM - tristate "CXL.mem: Memory Devices" +config CXL_PCI + tristate "PCI manageability" default CXL_BUS help - The CXL.mem protocol allows a device to act as a provider of - "System RAM" and/or "Persistent Memory" that is fully coherent - as if the memory was attached to the typical CPU memory - controller. + The CXL specification defines a set of interfaces which are controlled + through well known PCI configuration mechanisms. Such access is + referred to CXL.io in the specification. Say 'y/m' to enable a driver that will attach to CXL.mem devices for configuration and management primarily via the mailbox interface. See @@ -31,7 +30,7 @@ config CXL_MEM config CXL_MEM_RAW_COMMANDS bool "RAW Command Interface for Memory Devices" - depends on CXL_MEM + depends on CXL_PCI help Enable CXL RAW command interface. diff --git a/drivers/cxl/Makefile b/drivers/cxl/Makefile index d1aaabc940f3..cf07ae6cea17 100644 --- a/drivers/cxl/Makefile +++ b/drivers/cxl/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_CXL_BUS) += core/ -obj-$(CONFIG_CXL_MEM) += cxl_pci.o +obj-$(CONFIG_CXL_PCI) += cxl_pci.o obj-$(CONFIG_CXL_ACPI) += cxl_acpi.o obj-$(CONFIG_CXL_PMEM) += cxl_pmem.o