@@ -7,6 +7,7 @@
#include <linux/acpi.h>
#include <linux/pci.h>
#include "cxl.h"
+#include "pci.h"
static struct acpi_table_header *acpi_cedt;
@@ -206,11 +207,13 @@ static resource_size_t get_chbcr(struct acpi_cedt_chbs *chbs)
__mock int match_add_root_ports(struct pci_dev *pdev, void *data)
{
+ resource_size_t creg = CXL_RESOURCE_NONE;
struct cxl_walk_context *ctx = data;
struct pci_bus *root_bus = ctx->root;
struct cxl_port *port = ctx->port;
int type = pci_pcie_type(pdev);
struct device *dev = ctx->dev;
+ struct cxl_register_map map;
u32 lnkcap, port_num;
int rc;
@@ -224,9 +227,12 @@ __mock int match_add_root_ports(struct pci_dev *pdev, void *data)
&lnkcap) != PCIBIOS_SUCCESSFUL)
return 0;
- /* TODO walk DVSEC to find component register base */
+ rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+ if (!rc)
+ creg = cxl_reg_block(pdev, &map);
+
port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap);
- rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE);
+ rc = cxl_add_dport(port, &pdev->dev, port_num, creg);
if (rc) {
ctx->error = rc;
return rc;
@@ -31,4 +31,8 @@ enum cxl_regloc_type {
#define CXL_REGLOC_RBI_MASK GENMASK(15, 8)
#define CXL_REGLOC_ADDR_MASK GENMASK(31, 16)
+#define cxl_reg_block(pdev, map) \
+ ((resource_size_t)(pci_resource_start(pdev, (map)->barno) + \
+ (map)->block_offset))
+
#endif /* __CXL_PCI_H__ */
With the addition of cxl_find_register_block() in cxl_core, it becomes trivial to complete the TODO left for mapping the component registers of root ports. None of the CXL drivers currently use component registers of downstream ports (which is what a CXL 2.0 Root Port is). As such, there should be no functional change. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- drivers/cxl/acpi.c | 10 ++++++++-- drivers/cxl/pci.h | 4 ++++ 2 files changed, 12 insertions(+), 2 deletions(-)