Message ID | 20211022183709.1199701-18-ben.widawsky@intel.com |
---|---|
State | New, archived |
Headers | show
Return-Path: <linux-cxl-owner@kernel.org> X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8586EC433FE for <linux-cxl@archiver.kernel.org>; Fri, 22 Oct 2021 18:37:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6D27960E8C for <linux-cxl@archiver.kernel.org>; Fri, 22 Oct 2021 18:37:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233994AbhJVSji (ORCPT <rfc822;linux-cxl@archiver.kernel.org>); Fri, 22 Oct 2021 14:39:38 -0400 Received: from mga02.intel.com ([134.134.136.20]:5577 "EHLO mga02.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233930AbhJVSjg (ORCPT <rfc822;linux-cxl@vger.kernel.org>); Fri, 22 Oct 2021 14:39:36 -0400 X-IronPort-AV: E=McAfee;i="6200,9189,10145"; a="216528959" X-IronPort-AV: E=Sophos;i="5.87,173,1631602800"; d="scan'208";a="216528959" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2021 11:37:18 -0700 X-IronPort-AV: E=Sophos;i="5.87,173,1631602800"; d="scan'208";a="445854680" Received: from aagregor-mobl3.amr.corp.intel.com (HELO bad-guy.kumite) ([10.252.134.35]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2021 11:37:18 -0700 From: Ben Widawsky <ben.widawsky@intel.com> To: linux-cxl@vger.kernel.org, Chet Douglas <chet.r.douglas@intel.com> Cc: Ben Widawsky <ben.widawsky@intel.com>, Alison Schofield <alison.schofield@intel.com>, Dan Williams <dan.j.williams@intel.com>, Ira Weiny <ira.weiny@intel.com>, Jonathan Cameron <Jonathan.Cameron@Huawei.com>, Vishal Verma <vishal.l.verma@intel.com> Subject: [RFC PATCH v2 17/28] cxl: Disable switch hierarchies for now Date: Fri, 22 Oct 2021 11:36:58 -0700 Message-Id: <20211022183709.1199701-18-ben.widawsky@intel.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211022183709.1199701-1-ben.widawsky@intel.com> References: <20211022183709.1199701-1-ben.widawsky@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: <linux-cxl.vger.kernel.org> X-Mailing-List: linux-cxl@vger.kernel.org |
Series |
CXL Region Creation / HDM decoder programming
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diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 97092b9b748d..0b0272576e55 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -121,6 +121,11 @@ static int cxl_mem_probe(struct device *dev) goto out; } + /* FIXME: Add true switch support */ + dev_err(dev, "Devices behind switches are currently unsupported\n"); + rc = -ENODEV; + goto err_out; + /* Walk down from the root port and add all switches */ cxl_scan_ports(ctx.root_port);
Switches aren't supported by the region driver yet. If a device finds itself under a switch it will not bind a driver so that it cannot be used later for region creation/configuration. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- drivers/cxl/mem.c | 5 +++++ 1 file changed, 5 insertions(+)