Message ID | 20211022183709.1199701-4-ben.widawsky@intel.com |
---|---|
State | New, archived |
Headers | show |
Series | CXL Region Creation / HDM decoder programming | expand |
On Fri, Oct 22, 2021 at 11:37 AM Ben Widawsky <ben.widawsky@intel.com> wrote: > > With the addition of cxl_find_register_block() in cxl_core, it becomes > trivial to complete the TODO left for mapping the component registers of > root ports. None of the CXL drivers currently use component registers of > downstream ports (which is what a CXL 2.0 Root Port is). As such, there > should be no functional change. Oh, I forgot that cxl_acpi had this todo, I think it would be best to fold this with the previous patch so that it makes a complete story. > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > --- > drivers/cxl/acpi.c | 10 ++++++++-- > drivers/cxl/pci.h | 4 ++++ > 2 files changed, 12 insertions(+), 2 deletions(-) > > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c > index af1c6c1875ac..7d13e7f0aefc 100644 > --- a/drivers/cxl/acpi.c > +++ b/drivers/cxl/acpi.c > @@ -7,6 +7,7 @@ > #include <linux/acpi.h> > #include <linux/pci.h> > #include "cxl.h" > +#include "pci.h" > > static struct acpi_table_header *acpi_cedt; > > @@ -206,11 +207,13 @@ static resource_size_t get_chbcr(struct acpi_cedt_chbs *chbs) > > __mock int match_add_root_ports(struct pci_dev *pdev, void *data) > { > + resource_size_t creg = CXL_RESOURCE_NONE; > struct cxl_walk_context *ctx = data; > struct pci_bus *root_bus = ctx->root; > struct cxl_port *port = ctx->port; > int type = pci_pcie_type(pdev); > struct device *dev = ctx->dev; > + struct cxl_register_map map; > u32 lnkcap, port_num; > int rc; > > @@ -224,9 +227,12 @@ __mock int match_add_root_ports(struct pci_dev *pdev, void *data) > &lnkcap) != PCIBIOS_SUCCESSFUL) > return 0; > > - /* TODO walk DVSEC to find component register base */ > + rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map); > + if (!rc) > + creg = cxl_reg_block(pdev, &map); > + > port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); > - rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE); > + rc = cxl_add_dport(port, &pdev->dev, port_num, creg); > if (rc) { > ctx->error = rc; > return rc; > diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h > index 7d3e4bf06b45..12fdcb1b14e5 100644 > --- a/drivers/cxl/pci.h > +++ b/drivers/cxl/pci.h > @@ -31,4 +31,8 @@ enum cxl_regloc_type { > #define CXL_REGLOC_RBI_MASK GENMASK(15, 8) > #define CXL_REGLOC_ADDR_MASK GENMASK(31, 16) > > +#define cxl_reg_block(pdev, map) \ > + ((resource_size_t)(pci_resource_start(pdev, (map)->barno) + \ > + (map)->block_offset)) > + > #endif /* __CXL_PCI_H__ */ > -- > 2.33.1 >
diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c index af1c6c1875ac..7d13e7f0aefc 100644 --- a/drivers/cxl/acpi.c +++ b/drivers/cxl/acpi.c @@ -7,6 +7,7 @@ #include <linux/acpi.h> #include <linux/pci.h> #include "cxl.h" +#include "pci.h" static struct acpi_table_header *acpi_cedt; @@ -206,11 +207,13 @@ static resource_size_t get_chbcr(struct acpi_cedt_chbs *chbs) __mock int match_add_root_ports(struct pci_dev *pdev, void *data) { + resource_size_t creg = CXL_RESOURCE_NONE; struct cxl_walk_context *ctx = data; struct pci_bus *root_bus = ctx->root; struct cxl_port *port = ctx->port; int type = pci_pcie_type(pdev); struct device *dev = ctx->dev; + struct cxl_register_map map; u32 lnkcap, port_num; int rc; @@ -224,9 +227,12 @@ __mock int match_add_root_ports(struct pci_dev *pdev, void *data) &lnkcap) != PCIBIOS_SUCCESSFUL) return 0; - /* TODO walk DVSEC to find component register base */ + rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map); + if (!rc) + creg = cxl_reg_block(pdev, &map); + port_num = FIELD_GET(PCI_EXP_LNKCAP_PN, lnkcap); - rc = cxl_add_dport(port, &pdev->dev, port_num, CXL_RESOURCE_NONE); + rc = cxl_add_dport(port, &pdev->dev, port_num, creg); if (rc) { ctx->error = rc; return rc; diff --git a/drivers/cxl/pci.h b/drivers/cxl/pci.h index 7d3e4bf06b45..12fdcb1b14e5 100644 --- a/drivers/cxl/pci.h +++ b/drivers/cxl/pci.h @@ -31,4 +31,8 @@ enum cxl_regloc_type { #define CXL_REGLOC_RBI_MASK GENMASK(15, 8) #define CXL_REGLOC_ADDR_MASK GENMASK(31, 16) +#define cxl_reg_block(pdev, map) \ + ((resource_size_t)(pci_resource_start(pdev, (map)->barno) + \ + (map)->block_offset)) + #endif /* __CXL_PCI_H__ */
With the addition of cxl_find_register_block() in cxl_core, it becomes trivial to complete the TODO left for mapping the component registers of root ports. None of the CXL drivers currently use component registers of downstream ports (which is what a CXL 2.0 Root Port is). As such, there should be no functional change. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- drivers/cxl/acpi.c | 10 ++++++++-- drivers/cxl/pci.h | 4 ++++ 2 files changed, 12 insertions(+), 2 deletions(-)