| Message ID | 20211129214721.1668325-5-ben.widawsky@intel.com |
|---|---|
| State | New, archived |
| Headers | show |
| Series | CXL port prep work | expand |
On Mon, 29 Nov 2021 13:47:16 -0800 Ben Widawsky <ben.widawsky@intel.com> wrote: > The original driver implementation used the doorbell timeout for the > Mailbox Interface Ready bit to piggy back off of, since the latter > doesn't have a defined timeout. This functionality, introduced in commit > 8adaf747c9f0 ("cxl/mem: Find device capabilities"), can now be improved > since a timeout has been defined with an ECN to the 2.0 spec. > > While devices implemented prior to the ECN could have an arbitrarily > long wait and still be within spec, the max ECN value (256s) is chosen > as the default for all devices. All vendors in the consortium agreed to > this amount and so it is reasonable to assume no devices made will > exceed this amount. Update the description to talk about the 60 seconds choice. I'm fine with 60 seconds, but I can see it being controversial... > > Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> > > --- > Changes since v1: > - Use 60 seconds for timeout instead of 256 (Dan) > --- > drivers/cxl/pci.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index 6c8d09fb3a17..b28c220d48ea 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -2,6 +2,7 @@ > /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ > #include <linux/io-64-nonatomic-lo-hi.h> > #include <linux/module.h> > +#include <linux/delay.h> > #include <linux/sizes.h> > #include <linux/mutex.h> > #include <linux/list.h> > @@ -298,6 +299,38 @@ static int cxl_pci_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *c > static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds) > { > const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); > + unsigned long timeout; > + u64 md_status; > + int rc; > + > + /* > + * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to > + * dictate how long to wait for the mailbox to become ready. The new > + * field allows the device to tell software the amount of time to wait > + * before mailbox ready. This field allows for up to 255 seconds. 255 > + * seconds is unreasonable long, and longer than other default timeouts > + * in the OS. Use the more sane, 60 seconds instead. > + * > + * 100ms is chosen as the specified pause as it is the value used in the > + * CXL Type 3 Memory Device Software Guide. > + */ > + timeout = jiffies + 60 * HZ; > + > + rc = check_device_status(cxlds); > + if (rc) > + return rc; > + > + do { > + md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); > + if (md_status & CXLMDEV_MBOX_IF_READY) > + break; > + if (msleep_interruptible(100)) > + break; > + } while (!time_after(jiffies, timeout)); > + > + /* It's assumed that once the interface is ready, it will remain ready. */ > + if (!(md_status & CXLMDEV_MBOX_IF_READY)) > + return -EIO; > > cxlds->mbox_send = cxl_pci_mbox_send; > cxlds->payload_size =
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 6c8d09fb3a17..b28c220d48ea 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -2,6 +2,7 @@ /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ #include <linux/io-64-nonatomic-lo-hi.h> #include <linux/module.h> +#include <linux/delay.h> #include <linux/sizes.h> #include <linux/mutex.h> #include <linux/list.h> @@ -298,6 +299,38 @@ static int cxl_pci_mbox_send(struct cxl_dev_state *cxlds, struct cxl_mbox_cmd *c static int cxl_pci_setup_mailbox(struct cxl_dev_state *cxlds) { const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); + unsigned long timeout; + u64 md_status; + int rc; + + /* + * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to + * dictate how long to wait for the mailbox to become ready. The new + * field allows the device to tell software the amount of time to wait + * before mailbox ready. This field allows for up to 255 seconds. 255 + * seconds is unreasonable long, and longer than other default timeouts + * in the OS. Use the more sane, 60 seconds instead. + * + * 100ms is chosen as the specified pause as it is the value used in the + * CXL Type 3 Memory Device Software Guide. + */ + timeout = jiffies + 60 * HZ; + + rc = check_device_status(cxlds); + if (rc) + return rc; + + do { + md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); + if (md_status & CXLMDEV_MBOX_IF_READY) + break; + if (msleep_interruptible(100)) + break; + } while (!time_after(jiffies, timeout)); + + /* It's assumed that once the interface is ready, it will remain ready. */ + if (!(md_status & CXLMDEV_MBOX_IF_READY)) + return -EIO; cxlds->mbox_send = cxl_pci_mbox_send; cxlds->payload_size =
The original driver implementation used the doorbell timeout for the Mailbox Interface Ready bit to piggy back off of, since the latter doesn't have a defined timeout. This functionality, introduced in commit 8adaf747c9f0 ("cxl/mem: Find device capabilities"), can now be improved since a timeout has been defined with an ECN to the 2.0 spec. While devices implemented prior to the ECN could have an arbitrarily long wait and still be within spec, the max ECN value (256s) is chosen as the default for all devices. All vendors in the consortium agreed to this amount and so it is reasonable to assume no devices made will exceed this amount. Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- Changes since v1: - Use 60 seconds for timeout instead of 256 (Dan) --- drivers/cxl/pci.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)