@@ -171,6 +171,7 @@ ForEachMacros:
- 'for_each_cpu_wrap'
- 'for_each_cxl_decoder_target'
- 'for_each_cxl_endpoint'
+ - 'for_each_cxl_endpoint_hb'
- 'for_each_dapm_widgets'
- 'for_each_dev_addr'
- 'for_each_dev_scope'
@@ -585,6 +585,7 @@ struct cxl_dport *cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
return ERR_PTR(-ENOMEM);
INIT_LIST_HEAD(&dport->list);
+ INIT_LIST_HEAD(&dport->verify_link);
dport->dport = get_device(dport_dev);
dport->port_id = port_id;
dport->component_reg_phys = component_reg_phys;
@@ -303,6 +303,7 @@ struct cxl_port {
* @port: reference to cxl_port that contains this downstream port
* @list: node for a cxl_port's list of cxl_dport instances
* @link_name: the name of the sysfs link from @port to @dport
+ * @verify_link: node used for hb root port verification
*/
struct cxl_dport {
struct device *dport;
@@ -311,6 +312,7 @@ struct cxl_dport {
struct cxl_port *port;
struct list_head list;
char link_name[CXL_TARGET_STRLEN];
+ struct list_head verify_link;
};
/**
@@ -4,6 +4,7 @@
#include <linux/genalloc.h>
#include <linux/device.h>
#include <linux/module.h>
+#include <linux/sort.h>
#include <linux/pci.h>
#include "cxlmem.h"
#include "region.h"
@@ -35,6 +36,12 @@
idx < region_ways(region); \
idx++, ep = (region)->config.targets[idx])
+#define for_each_cxl_endpoint_hb(ep, region, hb, idx) \
+ for (idx = 0, (ep) = (region)->config.targets[idx]; \
+ idx < region_ways(region); \
+ idx++, (ep) = (region)->config.targets[idx]) \
+ if (get_hostbridge(ep) == (hb))
+
#define for_each_cxl_decoder_target(target, decoder, idx) \
for (idx = 0, target = (decoder)->target[idx]; \
idx < (decoder)->nr_targets; \
@@ -279,6 +286,59 @@ static bool region_xhb_config_valid(const struct cxl_region *region,
return true;
}
+static struct cxl_dport *get_rp(struct cxl_memdev *ep)
+{
+ struct cxl_port *port, *parent_port = port = ep->port;
+ struct cxl_dport *dport;
+
+ while (!is_cxl_root(port)) {
+ parent_port = to_cxl_port(port->dev.parent);
+ if (parent_port->depth == 1)
+ list_for_each_entry(dport, &parent_port->dports, list)
+ if (dport->dport == port->uport->parent->parent)
+ return dport;
+ port = parent_port;
+ }
+
+ BUG();
+ return NULL;
+}
+
+static int get_num_root_ports(const struct cxl_region *region)
+{
+ struct cxl_memdev *endpoint;
+ struct cxl_dport *dport, *tmp;
+ int num_root_ports = 0;
+ LIST_HEAD(root_ports);
+ int idx;
+
+ for_each_cxl_endpoint(endpoint, region, idx) {
+ struct cxl_dport *root_port = get_rp(endpoint);
+
+ if (list_empty(&root_port->verify_link)) {
+ list_add_tail(&root_port->verify_link, &root_ports);
+ num_root_ports++;
+ }
+ }
+
+ list_for_each_entry_safe(dport, tmp, &root_ports, verify_link)
+ list_del_init(&dport->verify_link);
+
+ return num_root_ports;
+}
+
+static bool has_switch(const struct cxl_region *region)
+{
+ struct cxl_memdev *ep;
+ int i;
+
+ for_each_cxl_endpoint(ep, region, i)
+ if (ep->port->depth > 2)
+ return true;
+
+ return false;
+}
+
/**
* region_hb_rp_config_valid() - determine root port ordering is correct
* @rootd: root decoder for this @region
@@ -292,7 +352,67 @@ static bool region_xhb_config_valid(const struct cxl_region *region,
static bool region_hb_rp_config_valid(const struct cxl_region *region,
const struct cxl_decoder *rootd)
{
- /* TODO: */
+ const int num_root_ports = get_num_root_ports(region);
+ struct cxl_port *hbs[CXL_DECODER_MAX_INTERLEAVE];
+ int hb_count, i;
+
+ hb_count = get_unique_hostbridges(region, hbs);
+
+ /*
+ * Are all devices in this region on the same CXL Host Bridge
+ * Root Port?
+ */
+ if (num_root_ports == 1 && !has_switch(region))
+ return true;
+
+ for (i = 0; i < hb_count; i++) {
+ int idx, position_mask;
+ struct cxl_dport *rp;
+ struct cxl_port *hb;
+
+ /* Get next CXL Host Bridge this region spans */
+ hb = hbs[i];
+
+ /*
+ * Calculate the position mask: NumRootPorts = 2^PositionMask
+ * for this region.
+ *
+ * XXX: pos_mask is actually (1 << PositionMask) - 1
+ */
+ position_mask = (1 << (ilog2(num_root_ports))) - 1;
+
+ /*
+ * Calculate the PortGrouping for each device on this CXL Host
+ * Bridge Root Port:
+ * PortGrouping = RegionLabel.Position & PositionMask
+ */
+ list_for_each_entry(rp, &hb->dports, list) {
+ struct cxl_memdev *ep;
+ int port_grouping = -1;
+
+ for_each_cxl_endpoint_hb(ep, region, hb, idx) {
+ /* Only endpoints under the same root port */
+ if (get_rp(ep) != rp)
+ continue;
+
+ if (port_grouping == -1) {
+ port_grouping = idx & position_mask;
+ continue;
+ }
+
+ /*
+ * Do all devices in the region connected to this CXL
+ * Host Bridge Root Port have the same PortGrouping?
+ */
+ if ((idx & position_mask) != port_grouping) {
+ trace_hb_rp_valid(region,
+ "One or more devices are not connected to the correct Host Bridge Root Port\n");
+ return false;
+ }
+ }
+ }
+ }
+
return true;
}
@@ -41,6 +41,9 @@ DEFINE_EVENT(cxl_region_template, allocation_failed,
DEFINE_EVENT(cxl_region_template, xhb_valid,
TP_PROTO(const struct cxl_region *region, char *status),
TP_ARGS(region, status));
+DEFINE_EVENT(cxl_region_template, hb_rp_valid,
+ TP_PROTO(const struct cxl_region *region, char *status),
+ TP_ARGS(region, status));
#endif /* if !defined (__CXL_TRACE_H__) || defined(TRACE_HEADER_MULTI_READ) */
Host bridge root port verification determines if the device ordering in an interleave set can be programmed through the host bridges and switches. The algorithm implemented here is based on the CXL Type 3 Memory Device Software Guide, chapter 2.13.15 Signed-off-by: Ben Widawsky <ben.widawsky@intel.com> --- .clang-format | 1 + drivers/cxl/core/port.c | 1 + drivers/cxl/cxl.h | 2 + drivers/cxl/region.c | 122 +++++++++++++++++++++++++++++++++++++++- drivers/cxl/trace.h | 3 + 5 files changed, 128 insertions(+), 1 deletion(-)