From patchwork Tue Jul 5 15:49:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 12906780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1006BC43334 for ; Tue, 5 Jul 2022 15:51:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230440AbiGEPvo (ORCPT ); Tue, 5 Jul 2022 11:51:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46496 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232949AbiGEPvF (ORCPT ); Tue, 5 Jul 2022 11:51:05 -0400 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA66C18E15; Tue, 5 Jul 2022 08:50:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1657036207; x=1688572207; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xrFja2ADE5qtMfXc+jWS05OGzDhcloppZSGS/q+/bMI=; b=ZaSChbPZIUnrXjSTrZh5f4zwBGYHCLj7CBlpMfnOH1orRvsYom5HMR0m YrN56vH80LWa8Z4XrNGwmPoKxNJQg7QJRZwrjvqB18SpE5KKV63Z8lri9 oAFSy4S0i1d6C47oZK625X5PAE4a8nTxBSRF3C3zRDwBsMKp6baFSyB22 fOcTNTMzmLiZ/yuF2RVrxTtdBocL6Lbr7WRwFsr98hxyrPM3BFkhiNQpk kxutqCbIhBeNLW/IUJ8lCmSZNUpAiT6dl6IRj1qgOLswaVCNxBh9ouM3K DOdSTSaLDvJ6icNe65SVM/NkSf3TuDC5n2486atTR813PngBsieP4xFYb g==; X-IronPort-AV: E=McAfee;i="6400,9594,10398"; a="263810333" X-IronPort-AV: E=Sophos;i="5.92,247,1650956400"; d="scan'208";a="263810333" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2022 08:50:07 -0700 X-IronPort-AV: E=Sophos;i="5.92,247,1650956400"; d="scan'208";a="543003422" Received: from amangla-mobl.amr.corp.intel.com (HELO localhost) ([10.255.0.184]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Jul 2022 08:50:04 -0700 From: ira.weiny@intel.com To: Dan Williams , Bjorn Helgaas , Jonathan Cameron Cc: Ira Weiny , Lukas Wunner , Alison Schofield , Vishal Verma , Dave Jiang , Ben Widawsky , linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH V13 7/9] cxl/port: Introduce cxl_cdat_valid() Date: Tue, 5 Jul 2022 08:49:30 -0700 Message-Id: <20220705154932.2141021-8-ira.weiny@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220705154932.2141021-1-ira.weiny@intel.com> References: <20220705154932.2141021-1-ira.weiny@intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Ira Weiny The CDAT data is protected by a checksum and should be the proper length. Introduce cxl_cdat_valid() to validate the data. While at it check and store the sequence number. Signed-off-by: Ira Weiny --- Changes from V12 Jonathan: Remove unneeded rc check. Changes from V8 Move code to cxl/core/pci.c Changes from V6 Change name to cxl_cdat_valid() as this validates all the CDAT data not just the header Add error and debug prints Changes from V5 New patch, split out Update cdat_hdr_valid() Remove revision and cs field parsing There is no point in these Add seq check and debug print. --- drivers/cxl/cdat.h | 2 ++ drivers/cxl/core/pci.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/drivers/cxl/cdat.h b/drivers/cxl/cdat.h index c6a48ab326bf..39eb561081f2 100644 --- a/drivers/cxl/cdat.h +++ b/drivers/cxl/cdat.h @@ -91,10 +91,12 @@ * * @table: cache of CDAT table * @length: length of cached CDAT table + * @seq: Last read Sequence number of the CDAT table */ struct cxl_cdat { void *table; size_t length; + u32 seq; }; #endif /* !__CXL_CDAT_H__ */ diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 9232b806d051..0a1620c302e1 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -531,6 +531,40 @@ static int cxl_cdat_get_length(struct device *dev, return 0; } +static bool cxl_cdat_valid(struct device *dev, struct cxl_cdat *cdat) +{ + u32 *table = cdat->table; + u8 *data8 = cdat->table; + u32 length, seq; + u8 check; + int i; + + length = FIELD_GET(CDAT_HEADER_DW0_LENGTH, table[0]); + if ((length < CDAT_HEADER_LENGTH_BYTES) || (length > cdat->length)) { + dev_err(dev, "CDAT Invalid length %u (%zu-%zu)\n", length, + CDAT_HEADER_LENGTH_BYTES, cdat->length); + return false; + } + + for (check = 0, i = 0; i < length; i++) + check += data8[i]; + + dev_dbg(dev, "CDAT length %u CS %u\n", length, check); + if (check != 0) { + dev_err(dev, "CDAT Invalid checksum %u\n", check); + return false; + } + + seq = FIELD_GET(CDAT_HEADER_DW3_SEQUENCE, table[3]); + /* Store the sequence for now. */ + if (cdat->seq != seq) { + dev_info(dev, "CDAT seq change %x -> %x\n", cdat->seq, seq); + cdat->seq = seq; + } + + return true; +} + static int cxl_cdat_read_table(struct device *dev, struct pci_doe_mb *cdat_mb, struct cxl_cdat *cdat) @@ -583,6 +617,9 @@ static int cxl_cdat_read_table(struct device *dev, } } while (entry_handle != CXL_DOE_TABLE_ACCESS_LAST_ENTRY); + if (!cxl_cdat_valid(dev, cdat)) + return -EIO; + return 0; }