| Message ID | 20220926215711.2893286-3-ira.weiny@intel.com |
|---|---|
| State | Accepted |
| Commit | 487d828d751d90cf9ca594f45b02dd0e0d712b64 |
| Headers | show |
| Series | CXL: Taint user access to DOE mailbox config space | expand |
On Mon, 26 Sep 2022 14:57:11 -0700 ira.weiny@intel.com wrote: > From: Ira Weiny <ira.weiny@intel.com> > > The PCIE Data Object Exchange (DOE) mailbox is a protocol run over > configuration cycles. It assumes one initiator at a time. While the > kernel has control of the mailbox user space writes could interfere with > the kernel access. > > Mark DOE mailbox config space exclusive when iterated by the CXL driver. > > Signed-off-by: Ira Weiny <ira.weiny@intel.com> I wonder a bit on whether the failure should be fatal given that something very odd would be required for it to fail. I'm not that bothered though. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > --- > Changes from V2: > Jonathan: > s/PCI_DOE_CAP_SIZE/PCI_DOE_CAP_SIZEOF > Set PCI_DOE_CAP_SIZEOF directly > --- > drivers/cxl/pci.c | 5 +++++ > include/uapi/linux/pci_regs.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index faeb5d9d7a7a..621a0522b554 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -418,6 +418,11 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) > continue; > } > > + if (!pci_request_config_region_exclusive(pdev, off, > + PCI_DOE_CAP_SIZEOF, > + dev_name(dev))) > + pci_err(pdev, "Failed to exclude DOE registers\n"); > + > if (xa_insert(&cxlds->doe_mbs, off, doe_mb, GFP_KERNEL)) { > dev_err(dev, "xa_insert failed to insert MB @ %x\n", > off); > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 57b8e2ffb1dd..82a03ea954af 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -1119,6 +1119,7 @@ > #define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 /* Data Object Ready */ > #define PCI_DOE_WRITE 0x10 /* DOE Write Data Mailbox Register */ > #define PCI_DOE_READ 0x14 /* DOE Read Data Mailbox Register */ > +#define PCI_DOE_CAP_SIZEOF 0x18 /* Size of DOE register block */ > > /* DOE Data Object - note not actually registers */ > #define PCI_DOE_DATA_OBJECT_HEADER_1_VID 0x0000ffff
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index faeb5d9d7a7a..621a0522b554 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -418,6 +418,11 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) continue; } + if (!pci_request_config_region_exclusive(pdev, off, + PCI_DOE_CAP_SIZEOF, + dev_name(dev))) + pci_err(pdev, "Failed to exclude DOE registers\n"); + if (xa_insert(&cxlds->doe_mbs, off, doe_mb, GFP_KERNEL)) { dev_err(dev, "xa_insert failed to insert MB @ %x\n", off); diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 57b8e2ffb1dd..82a03ea954af 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1119,6 +1119,7 @@ #define PCI_DOE_STATUS_DATA_OBJECT_READY 0x80000000 /* Data Object Ready */ #define PCI_DOE_WRITE 0x10 /* DOE Write Data Mailbox Register */ #define PCI_DOE_READ 0x14 /* DOE Read Data Mailbox Register */ +#define PCI_DOE_CAP_SIZEOF 0x18 /* Size of DOE register block */ /* DOE Data Object - note not actually registers */ #define PCI_DOE_DATA_OBJECT_HEADER_1_VID 0x0000ffff