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Wysocki" , Len Brown , Jonathan Cameron , "Davidlohr Bueso" , Robert Richter Subject: [PATCH v2 12/12] cxl: Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH) Date: Tue, 18 Oct 2022 15:23:40 +0200 Message-ID: <20221018132341.76259-13-rrichter@amd.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20221018132341.76259-1-rrichter@amd.com> References: <20221018132341.76259-1-rrichter@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT078:EE_|BY5PR12MB4113:EE_ X-MS-Office365-Filtering-Correlation-Id: 54cd921f-b359-4d0c-667b-08dab10c298d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Es/Uqk0Pq4ACISn1odl+Wc75MKbuifwqpeiQv7f2PfsVWoPS0DFN3RU0doKYobmR5aeQKHti871q2gJDbe5vKqu0AteWKYqzC9Tdjwj+aL6nJC2H6GYHkNbQpU1uJvjnS/O1QcKBhfNw9IPDzjIKELCUf/VmTW5NpZIoynpFa9VypY2PEpiTJSRxWr+6brJG9ybtn8Hu+fpbU1L59ETvOTCeiC3NoCDnlQCgqwt+QfOMduTqnrsjeqRksbM78AFtskbF3xSSKPeYGwV9FKfZYgeiKO3j+LXL+v1Dp40dNuS0cVbxQkuiBubdyYM0flTzyWaUrfHOdXQb/MUglmdT9f2CfTYHlGHStvpo+Nh6Hu92rDEavrQBEOJLtMMSgNvokeFdTWQbZiU5rUEqB9FDi/78s6xErfcyivMGToUc5kXJqtPUwbs9s/deE/JjzeTFuqxkS2Uv+fLD0nzjyxiSynnarL9Fmi/Y6DiTzUgHhvHR8kkTKeVvyYOWLO72ZUuSFxXi1xASuO8fHVZaQfe3B/L4uQEEZo7lxheq7t39oxPQcWjd3qFFLOXbPTCskVsKfPzmuEjxek8G3+hnL1he6UWlCHe6VUSR4mvYDvvYqelyeii5SbKfM3nKDFzw04m190S/617BIw4LnynkSip/5EUfmeUmqITbXLVAHsqNvPmSLU+iHl1fbq9GyaBFbgkfD60fqCY3oS11DNfm3bIOS90DGTCxyIAAflnJ+aWbzee613qmFsDSOTVVSsy1X14GdFeiZqWdBOKXaeKOR5AtJscv8rlIUMJOwtdXt8uduIeLk+YpD2ISI8tKXpE3kqsM X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(136003)(346002)(39860400002)(396003)(451199015)(40470700004)(36840700001)(46966006)(336012)(83380400001)(81166007)(426003)(8936002)(356005)(36860700001)(47076005)(82740400003)(5660300002)(70206006)(41300700001)(8676002)(4326008)(82310400005)(70586007)(2906002)(7416002)(186003)(2616005)(1076003)(110136005)(26005)(54906003)(6666004)(40480700001)(316002)(478600001)(16526019)(40460700003)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Oct 2022 13:25:02.0734 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54cd921f-b359-4d0c-667b-08dab10c298d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4113 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The PCIe Software View of an RCH and RCD is different to VH mode. An RCD is paired with an RCH and shows up as RCiEP. Its downstream and upstream ports are hidden to the PCI hierarchy. This different PCI topology requires a different handling of RCHs. Extend devm_cxl_port_enumerate_dports() to support restricted hosts (RCH). If an RCH is detected, register its port as dport to the device. An RCH is found if the host's dev 0 func 0 devices is an RCiEP with an existing PCIe DVSEC for CXL Devices (ID 0000h). Signed-off-by: Robert Richter --- drivers/cxl/core/pci.c | 37 ++++++++++++++++++++++++++++++++++++- 1 file changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 667de4f125f6..a6b1a1501db3 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -48,6 +48,37 @@ static int pci_dev_add_dport(struct pci_dev *pdev, struct cxl_port *port, return 0; } +static int restricted_host_enumerate_dport(struct cxl_port *port, + struct pci_bus *bus) +{ + struct pci_dev *pdev; + bool is_restricted_host; + int rc; + + /* Check CXL DVSEC of dev 0 func 0 */ + pdev = pci_get_slot(bus, PCI_DEVFN(0, 0)); + + is_restricted_host = pdev + && (pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END) + && pci_find_dvsec_capability(pdev, + PCI_DVSEC_VENDOR_ID_CXL, + CXL_DVSEC_PCIE_DEVICE); + if (is_restricted_host) + rc = pci_dev_add_dport(pdev, port, CXL_RESOURCE_NONE); + + pci_dev_put(pdev); + + if (!is_restricted_host) + return 0; + + dev_dbg(bus->bridge, "CXL restricted host found\n"); + + if (rc) + return rc; + + return 1; +} + static int match_add_dports(struct pci_dev *pdev, void *data) { struct cxl_walk_context *ctx = data; @@ -91,11 +122,15 @@ int devm_cxl_port_enumerate_dports(struct cxl_port *port) { struct pci_bus *bus = cxl_port_to_pci_bus(port); struct cxl_walk_context ctx; - int type; + int type, count; if (!bus) return -ENXIO; + count = restricted_host_enumerate_dport(port, bus); + if (count) + return count; + if (pci_is_root_bus(bus)) type = PCI_EXP_TYPE_ROOT_PORT; else