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Fri, 21 Oct 2022 18:57:05 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT096.mail.protection.outlook.com (10.13.177.195) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5746.16 via Frontend Transport; Fri, 21 Oct 2022 18:57:05 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.31; Fri, 21 Oct 2022 13:57:04 -0500 From: Terry Bowman To: , , , , , CC: , , , , , , , , Subject: [PATCH 4/5] cxl/pci: Enable RCD dport AER reporting Date: Fri, 21 Oct 2022 13:56:14 -0500 Message-ID: <20221021185615.605233-5-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221021185615.605233-1-terry.bowman@amd.com> References: <20221021185615.605233-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT096:EE_|DS0PR12MB6416:EE_ X-MS-Office365-Filtering-Correlation-Id: 51e11ef2-2359-45fa-6a88-08dab3960c28 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Oct 2022 18:57:05.6319 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 51e11ef2-2359-45fa-6a88-08dab3960c28 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT096.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6416 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The RCD downport/upport include 'PCI express' capability with AER registers. The PCI subsystem is not aware of RCD downport/upport AER because the downport/upport are not enumerable devices. Since the downport/upport are not enumerable the existing PCIe AER logic to enable AER reporting does not apply. Add logic to the CXL driver to enable AER reporting in the RCRB 'PCI express' capability. These must be set for correctly reporting the PCIe AER errors to the RCEC or root port. Signed-off-by: Terry Bowman --- drivers/cxl/pci.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 7f717fb47a36..80a01b304efe 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -553,6 +553,17 @@ static resource_size_t cxl_get_dport_cap(struct cxl_memdev *cxlmd, int cap_id) return rcrb + offset; } +static void cxl_enable_dport_aer(struct cxl_memdev *cxlmd) +{ + struct cxl_register_map *map = &cxlmd->cxlds->aer_map; + u32 devctl_cap; + + devctl_cap = readl(map->base + PCI_EXP_DEVCTL); + devctl_cap |= (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | + PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE); + writel(devctl_cap, map->base + PCI_EXP_DEVCTL); +} + static int cxl_setup_dport_aer(struct cxl_memdev *cxlmd, resource_size_t cap_base) { struct cxl_register_map *map = &cxlmd->cxlds->aer_map; @@ -566,6 +577,8 @@ static int cxl_setup_dport_aer(struct cxl_memdev *cxlmd, resource_size_t cap_bas if (!map->base) return -ENOMEM; + cxl_enable_dport_aer(cxlmd); + return 0; }