| Message ID | 20221109104059.766720-6-rrichter@amd.com |
|---|---|
| State | New, archived |
| Headers | show |
| Series | cxl: Add support for Restricted CXL hosts (RCD mode) | expand |
Robert Richter wrote: > The Device 0, Function 0 DVSEC controls the CXL functionality of the > entire device. Add a check to prevent registration of any other PCI > device on the bus as a CXL memory device. Can you reference the specification wording that indicates that the OS needs to actively avoid these situations, or otherwise point to the real world scenario where this filtering is needed? > > Signed-off-by: Robert Richter <rrichter@amd.com> > --- > drivers/cxl/pci.c | 25 +++++++++++++++++++++++-- > 1 file changed, 23 insertions(+), 2 deletions(-) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index faeb5d9d7a7a..cc4f206f24b3 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -428,11 +428,26 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) > } > } > > +static int check_restricted_device(struct pci_dev *pdev, u16 pcie_dvsec) > +{ > + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_END) > + return 0; /* no RCD */ > + > + if (pdev->devfn == PCI_DEVFN(0, 0) && pcie_dvsec) > + return 0; /* ok */ > + > + dev_warn(&pdev->dev, "Skipping RCD: devfn=0x%02x dvsec=%u\n", s/0x%02x/%#02x/ > + pdev->devfn, pcie_dvsec); This looks like a dev_dbg() to me. Otherwise a warning will always fire on a benign condition. > + > + return -ENODEV; > +} > + > static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > { > struct cxl_register_map map; > struct cxl_memdev *cxlmd; > struct cxl_dev_state *cxlds; > + u16 pcie_dvsec; > int rc; > > /* > @@ -442,6 +457,13 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != > offsetof(struct cxl_regs, device_regs.memdev)); > > + pcie_dvsec = pci_find_dvsec_capability( > + pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); > + > + rc = check_restricted_device(pdev, pcie_dvsec); > + if (rc) > + return rc; > + > rc = pcim_enable_device(pdev); > if (rc) > return rc; > @@ -451,8 +473,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > return PTR_ERR(cxlds); > > cxlds->serial = pci_get_dsn(pdev); > - cxlds->cxl_dvsec = pci_find_dvsec_capability( > - pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); > + cxlds->cxl_dvsec = pcie_dvsec; > if (!cxlds->cxl_dvsec) > dev_warn(&pdev->dev, > "Device DVSEC not present, skip CXL.mem init\n"); > -- > 2.30.2 >
On 16.11.22 11:24:48, Dan Williams wrote: > Robert Richter wrote: > > The Device 0, Function 0 DVSEC controls the CXL functionality of the > > entire device. Add a check to prevent registration of any other PCI > > device on the bus as a CXL memory device. > > Can you reference the specification wording that indicates that the OS > needs to actively avoid these situations, or otherwise point to the real > world scenario where this filtering is needed? CXL 3.0 8.1.3 PCIe DVSEC for CXL Device """ An RCD creates a new PCIe enumeration hierarchy. As such, it spawns a new Root Bus and can expose one or more PCIe device numbers and function numbers at this bus number. These are exposed as Root Complex Integrated Endpoints (RCiEP). The PCIe Configuration Space of Device 0, Function 0 shall include the CXL PCIe DVSEC as shown in Figure 8-1. """ """ In either case, the capability, status, and control fields in Device 0, Function 0 DVSEC control the CXL functionality of the entire device. """ There are some other occurrences. I think this is even true for VH mode, as multiple CXL devices on the bus are exposed through multiple DSPs or Root Ports. Anyway, I limited this to an RCD only, esp. because its counterpart would be missing and thus port mapping would fail otherwise. See restricted_host_enumerate_dport() of this series. > > > > > Signed-off-by: Robert Richter <rrichter@amd.com> > > --- > > drivers/cxl/pci.c | 25 +++++++++++++++++++++++-- > > 1 file changed, 23 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > > index faeb5d9d7a7a..cc4f206f24b3 100644 > > --- a/drivers/cxl/pci.c > > +++ b/drivers/cxl/pci.c > > @@ -428,11 +428,26 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) > > } > > } > > > > +static int check_restricted_device(struct pci_dev *pdev, u16 pcie_dvsec) > > +{ > > + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_END) > > + return 0; /* no RCD */ > > + > > + if (pdev->devfn == PCI_DEVFN(0, 0) && pcie_dvsec) > > + return 0; /* ok */ > > + > > + dev_warn(&pdev->dev, "Skipping RCD: devfn=0x%02x dvsec=%u\n", > > s/0x%02x/%#02x/ > > > + pdev->devfn, pcie_dvsec); Ok. > This looks like a dev_dbg() to me. Otherwise a warning will always fire > on a benign condition. I have chosen dev_warn() here as this is a non-compliant unexpected behavior of the device. There are no (legal) cases this may happen. I suppose you are worried about spamming the console here, but that error should be reported somewhere and thus being visible. Note: There can be multiple devices on the bus, but those shouldn't have a CXL mem dev class code and the devices shouldn't being probed by cxl_pci_probe() which contains the check and later creates a cxlmd dev. -Robert
Robert Richter wrote: > On 16.11.22 11:24:48, Dan Williams wrote: > > Robert Richter wrote: > > > The Device 0, Function 0 DVSEC controls the CXL functionality of the > > > entire device. Add a check to prevent registration of any other PCI > > > device on the bus as a CXL memory device. > > > > Can you reference the specification wording that indicates that the OS > > needs to actively avoid these situations, or otherwise point to the real > > world scenario where this filtering is needed? > > CXL 3.0 > > 8.1.3 PCIe DVSEC for CXL Device > > """ > An RCD creates a new PCIe enumeration hierarchy. As such, it spawns a new Root Bus > and can expose one or more PCIe device numbers and function numbers at this bus > number. These are exposed as Root Complex Integrated Endpoints (RCiEP). The PCIe > Configuration Space of Device 0, Function 0 shall include the CXL PCIe DVSEC as shown > in Figure 8-1. > """ > > """ > In either case, the capability, status, and control fields in Device 0, Function 0 DVSEC > control the CXL functionality of the entire device. > """ > > There are some other occurrences. I think this is even true for VH > mode, as multiple CXL devices on the bus are exposed through multiple > DSPs or Root Ports. > > Anyway, I limited this to an RCD only, esp. because its counterpart > would be missing and thus port mapping would fail otherwise. See > restricted_host_enumerate_dport() of this series. > > > > > > > > > Signed-off-by: Robert Richter <rrichter@amd.com> > > > --- > > > drivers/cxl/pci.c | 25 +++++++++++++++++++++++-- > > > 1 file changed, 23 insertions(+), 2 deletions(-) > > > > > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > > > index faeb5d9d7a7a..cc4f206f24b3 100644 > > > --- a/drivers/cxl/pci.c > > > +++ b/drivers/cxl/pci.c > > > @@ -428,11 +428,26 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) > > > } > > > } > > > > > > +static int check_restricted_device(struct pci_dev *pdev, u16 pcie_dvsec) > > > +{ > > > + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_END) > > > + return 0; /* no RCD */ > > > + > > > + if (pdev->devfn == PCI_DEVFN(0, 0) && pcie_dvsec) > > > + return 0; /* ok */ > > > + > > > + dev_warn(&pdev->dev, "Skipping RCD: devfn=0x%02x dvsec=%u\n", > > > > s/0x%02x/%#02x/ > > > > > + pdev->devfn, pcie_dvsec); > > Ok. > > > This looks like a dev_dbg() to me. Otherwise a warning will always fire > > on a benign condition. > > I have chosen dev_warn() here as this is a non-compliant unexpected > behavior of the device. There are no (legal) cases this may happen. I > suppose you are worried about spamming the console here, but that > error should be reported somewhere and thus being visible. There are so many spec illegal values and conditions that the driver could checki, but does not. The reason I am poking here is why does the driver need to be explicit about *this* illegal condition versus all the other potential conditions? What is the practical end user impact if Linux does not include this change? For example, if it is just one vendor that made this mistake that can be an explicit quirk. A dev_warn() is not necessary for simple quirks.
On 17.11.22 09:27:23, Dan Williams wrote: > Robert Richter wrote: > > On 16.11.22 11:24:48, Dan Williams wrote: > > > Robert Richter wrote: > > > > The Device 0, Function 0 DVSEC controls the CXL functionality of the > > > > entire device. Add a check to prevent registration of any other PCI > > > > device on the bus as a CXL memory device. > > > > > > Can you reference the specification wording that indicates that the OS > > > needs to actively avoid these situations, or otherwise point to the real > > > world scenario where this filtering is needed? > > > > CXL 3.0 > > > > 8.1.3 PCIe DVSEC for CXL Device > > > > """ > > An RCD creates a new PCIe enumeration hierarchy. As such, it spawns a new Root Bus > > and can expose one or more PCIe device numbers and function numbers at this bus > > number. These are exposed as Root Complex Integrated Endpoints (RCiEP). The PCIe > > Configuration Space of Device 0, Function 0 shall include the CXL PCIe DVSEC as shown > > in Figure 8-1. > > """ > > > > """ > > In either case, the capability, status, and control fields in Device 0, Function 0 DVSEC > > control the CXL functionality of the entire device. > > """ > > > > There are some other occurrences. I think this is even true for VH > > mode, as multiple CXL devices on the bus are exposed through multiple > > DSPs or Root Ports. > > > > Anyway, I limited this to an RCD only, esp. because its counterpart > > would be missing and thus port mapping would fail otherwise. See > > restricted_host_enumerate_dport() of this series. > > > > > > > > > > > > > Signed-off-by: Robert Richter <rrichter@amd.com> > > > > --- > > > > drivers/cxl/pci.c | 25 +++++++++++++++++++++++-- > > > > 1 file changed, 23 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > > > > index faeb5d9d7a7a..cc4f206f24b3 100644 > > > > --- a/drivers/cxl/pci.c > > > > +++ b/drivers/cxl/pci.c > > > > @@ -428,11 +428,26 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) > > > > } > > > > } > > > > > > > > +static int check_restricted_device(struct pci_dev *pdev, u16 pcie_dvsec) > > > > +{ > > > > + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_END) > > > > + return 0; /* no RCD */ > > > > + > > > > + if (pdev->devfn == PCI_DEVFN(0, 0) && pcie_dvsec) > > > > + return 0; /* ok */ > > > > + > > > > + dev_warn(&pdev->dev, "Skipping RCD: devfn=0x%02x dvsec=%u\n", > > > > > > s/0x%02x/%#02x/ > > > > > > > + pdev->devfn, pcie_dvsec); > > > > Ok. > > > > > This looks like a dev_dbg() to me. Otherwise a warning will always fire > > > on a benign condition. > > > > I have chosen dev_warn() here as this is a non-compliant unexpected > > behavior of the device. There are no (legal) cases this may happen. I > > suppose you are worried about spamming the console here, but that > > error should be reported somewhere and thus being visible. > > There are so many spec illegal values and conditions that the driver > could checki, but does not. The reason I am poking here is why does the > driver need to be explicit about *this* illegal condition versus all the > other potential conditions? What is the practical end user impact if > Linux does not include this change? For example, if it is just one > vendor that made this mistake that can be an explicit quirk. > > A dev_warn() is not necessary for simple quirks. This is not simply a cross check, the driver prevents enablement of CXL mem devs other than PCI_DEVFN(0, 0). It shouldn't silently drop out then. It's a device malfunction which should appropriate reported and not only visible if dbg is enabled. As written above, the check is necessary as the counterpart is missing otherwise and init would fail later with a more obfuscating error message. -Robert
Robert Richter wrote: > On 17.11.22 09:27:23, Dan Williams wrote: > > Robert Richter wrote: > > > On 16.11.22 11:24:48, Dan Williams wrote: > > > > Robert Richter wrote: > > > > > The Device 0, Function 0 DVSEC controls the CXL functionality of the > > > > > entire device. Add a check to prevent registration of any other PCI > > > > > device on the bus as a CXL memory device. > > > > > > > > Can you reference the specification wording that indicates that the OS > > > > needs to actively avoid these situations, or otherwise point to the real > > > > world scenario where this filtering is needed? > > > > > > CXL 3.0 > > > > > > 8.1.3 PCIe DVSEC for CXL Device > > > > > > """ > > > An RCD creates a new PCIe enumeration hierarchy. As such, it spawns a new Root Bus > > > and can expose one or more PCIe device numbers and function numbers at this bus > > > number. These are exposed as Root Complex Integrated Endpoints (RCiEP). The PCIe > > > Configuration Space of Device 0, Function 0 shall include the CXL PCIe DVSEC as shown > > > in Figure 8-1. > > > """ > > > > > > """ > > > In either case, the capability, status, and control fields in Device 0, Function 0 DVSEC > > > control the CXL functionality of the entire device. > > > """ > > > > > > There are some other occurrences. I think this is even true for VH > > > mode, as multiple CXL devices on the bus are exposed through multiple > > > DSPs or Root Ports. > > > > > > Anyway, I limited this to an RCD only, esp. because its counterpart > > > would be missing and thus port mapping would fail otherwise. See > > > restricted_host_enumerate_dport() of this series. > > > > > > > > > > > > > > > > > Signed-off-by: Robert Richter <rrichter@amd.com> > > > > > --- > > > > > drivers/cxl/pci.c | 25 +++++++++++++++++++++++-- > > > > > 1 file changed, 23 insertions(+), 2 deletions(-) > > > > > > > > > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > > > > > index faeb5d9d7a7a..cc4f206f24b3 100644 > > > > > --- a/drivers/cxl/pci.c > > > > > +++ b/drivers/cxl/pci.c > > > > > @@ -428,11 +428,26 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) > > > > > } > > > > > } > > > > > > > > > > +static int check_restricted_device(struct pci_dev *pdev, u16 pcie_dvsec) > > > > > +{ > > > > > + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_END) > > > > > + return 0; /* no RCD */ > > > > > + > > > > > + if (pdev->devfn == PCI_DEVFN(0, 0) && pcie_dvsec) > > > > > + return 0; /* ok */ > > > > > + > > > > > + dev_warn(&pdev->dev, "Skipping RCD: devfn=0x%02x dvsec=%u\n", > > > > > > > > s/0x%02x/%#02x/ > > > > > > > > > + pdev->devfn, pcie_dvsec); > > > > > > Ok. > > > > > > > This looks like a dev_dbg() to me. Otherwise a warning will always fire > > > > on a benign condition. > > > > > > I have chosen dev_warn() here as this is a non-compliant unexpected > > > behavior of the device. There are no (legal) cases this may happen. I > > > suppose you are worried about spamming the console here, but that > > > error should be reported somewhere and thus being visible. > > > > There are so many spec illegal values and conditions that the driver > > could checki, but does not. The reason I am poking here is why does the > > driver need to be explicit about *this* illegal condition versus all the > > other potential conditions? What is the practical end user impact if > > Linux does not include this change? For example, if it is just one > > vendor that made this mistake that can be an explicit quirk. > > > > A dev_warn() is not necessary for simple quirks. > > This is not simply a cross check, the driver prevents enablement of > CXL mem devs other than PCI_DEVFN(0, 0). It shouldn't silently drop > out then. It's a device malfunction which should appropriate reported > and not only visible if dbg is enabled. > > As written above, the check is necessary as the counterpart is missing It is only necessary if this condition happens in practice, not a theoretically. So I am asking, are you seeing this with an actual device that someone will use in production? If so, that's what pci quirks are for to keep those workarounds organized in a common location.
On 18.11.22 08:55:13, Dan Williams wrote: > Robert Richter wrote: > > On 17.11.22 09:27:23, Dan Williams wrote: > > > Robert Richter wrote: > > > > On 16.11.22 11:24:48, Dan Williams wrote: > > > > > Robert Richter wrote: > > > > > > The Device 0, Function 0 DVSEC controls the CXL functionality of the > > > > > > entire device. Add a check to prevent registration of any other PCI > > > > > > device on the bus as a CXL memory device. > > > > > > > > > > Can you reference the specification wording that indicates that the OS > > > > > needs to actively avoid these situations, or otherwise point to the real > > > > > world scenario where this filtering is needed? > > > > > > > > CXL 3.0 > > > > > > > > 8.1.3 PCIe DVSEC for CXL Device > > > > > > > > """ > > > > An RCD creates a new PCIe enumeration hierarchy. As such, it spawns a new Root Bus > > > > and can expose one or more PCIe device numbers and function numbers at this bus > > > > number. These are exposed as Root Complex Integrated Endpoints (RCiEP). The PCIe > > > > Configuration Space of Device 0, Function 0 shall include the CXL PCIe DVSEC as shown > > > > in Figure 8-1. > > > > """ > > > > > > > > """ > > > > In either case, the capability, status, and control fields in Device 0, Function 0 DVSEC > > > > control the CXL functionality of the entire device. > > > > """ > > > > > > > > There are some other occurrences. I think this is even true for VH > > > > mode, as multiple CXL devices on the bus are exposed through multiple > > > > DSPs or Root Ports. > > > > > > > > Anyway, I limited this to an RCD only, esp. because its counterpart > > > > would be missing and thus port mapping would fail otherwise. See > > > > restricted_host_enumerate_dport() of this series. > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Robert Richter <rrichter@amd.com> > > > > > > --- > > > > > > drivers/cxl/pci.c | 25 +++++++++++++++++++++++-- > > > > > > 1 file changed, 23 insertions(+), 2 deletions(-) > > > > > > > > > > > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > > > > > > index faeb5d9d7a7a..cc4f206f24b3 100644 > > > > > > --- a/drivers/cxl/pci.c > > > > > > +++ b/drivers/cxl/pci.c > > > > > > @@ -428,11 +428,26 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) > > > > > > } > > > > > > } > > > > > > > > > > > > +static int check_restricted_device(struct pci_dev *pdev, u16 pcie_dvsec) > > > > > > +{ > > > > > > + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_END) > > > > > > + return 0; /* no RCD */ > > > > > > + > > > > > > + if (pdev->devfn == PCI_DEVFN(0, 0) && pcie_dvsec) > > > > > > + return 0; /* ok */ > > > > > > + > > > > > > + dev_warn(&pdev->dev, "Skipping RCD: devfn=0x%02x dvsec=%u\n", > > > > > > > > > > s/0x%02x/%#02x/ > > > > > > > > > > > + pdev->devfn, pcie_dvsec); > > > > > > > > Ok. > > > > > > > > > This looks like a dev_dbg() to me. Otherwise a warning will always fire > > > > > on a benign condition. > > > > > > > > I have chosen dev_warn() here as this is a non-compliant unexpected > > > > behavior of the device. There are no (legal) cases this may happen. I > > > > suppose you are worried about spamming the console here, but that > > > > error should be reported somewhere and thus being visible. > > > > > > There are so many spec illegal values and conditions that the driver > > > could checki, but does not. The reason I am poking here is why does the > > > driver need to be explicit about *this* illegal condition versus all the > > > other potential conditions? What is the practical end user impact if > > > Linux does not include this change? For example, if it is just one > > > vendor that made this mistake that can be an explicit quirk. > > > > > > A dev_warn() is not necessary for simple quirks. > > > > This is not simply a cross check, the driver prevents enablement of > > CXL mem devs other than PCI_DEVFN(0, 0). It shouldn't silently drop > > out then. It's a device malfunction which should appropriate reported > > and not only visible if dbg is enabled. > > > > As written above, the check is necessary as the counterpart is missing > > It is only necessary if this condition happens in practice, not a > theoretically. So I am asking, are you seeing this with an actual device > that someone will use in production? If so, that's what pci quirks are > for to keep those workarounds organized in a common location. I can make it a dev_dbg() message. But I do not understand the ratio behind this. This is not a quirk nor a workaround or a fix for something. The likely paths are the conditions checked that return 0. Only if the unlikely case happens where a CXL mem dev is not a dev 0, func 0, a warning is shown to inform the user that this dev is not enabled. So yes, this might be theoretical similar to that a driver cannot allocate memory. But why not print this as a warning message then? Anyway, let's make it a dev_dbg(). Thanks, -Robert
Robert Richter wrote: > On 18.11.22 08:55:13, Dan Williams wrote: > > Robert Richter wrote: > > > On 17.11.22 09:27:23, Dan Williams wrote: > > > > Robert Richter wrote: > > > > > On 16.11.22 11:24:48, Dan Williams wrote: > > > > > > Robert Richter wrote: > > > > > > > The Device 0, Function 0 DVSEC controls the CXL functionality of the > > > > > > > entire device. Add a check to prevent registration of any other PCI > > > > > > > device on the bus as a CXL memory device. > > > > > > > > > > > > Can you reference the specification wording that indicates that the OS > > > > > > needs to actively avoid these situations, or otherwise point to the real > > > > > > world scenario where this filtering is needed? > > > > > > > > > > CXL 3.0 > > > > > > > > > > 8.1.3 PCIe DVSEC for CXL Device > > > > > > > > > > """ > > > > > An RCD creates a new PCIe enumeration hierarchy. As such, it spawns a new Root Bus > > > > > and can expose one or more PCIe device numbers and function numbers at this bus > > > > > number. These are exposed as Root Complex Integrated Endpoints (RCiEP). The PCIe > > > > > Configuration Space of Device 0, Function 0 shall include the CXL PCIe DVSEC as shown > > > > > in Figure 8-1. > > > > > """ > > > > > > > > > > """ > > > > > In either case, the capability, status, and control fields in Device 0, Function 0 DVSEC > > > > > control the CXL functionality of the entire device. > > > > > """ > > > > > > > > > > There are some other occurrences. I think this is even true for VH > > > > > mode, as multiple CXL devices on the bus are exposed through multiple > > > > > DSPs or Root Ports. > > > > > > > > > > Anyway, I limited this to an RCD only, esp. because its counterpart > > > > > would be missing and thus port mapping would fail otherwise. See > > > > > restricted_host_enumerate_dport() of this series. > > > > > > > > > > > > > > > > > > > > > > > > > Signed-off-by: Robert Richter <rrichter@amd.com> > > > > > > > --- > > > > > > > drivers/cxl/pci.c | 25 +++++++++++++++++++++++-- > > > > > > > 1 file changed, 23 insertions(+), 2 deletions(-) > > > > > > > > > > > > > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > > > > > > > index faeb5d9d7a7a..cc4f206f24b3 100644 > > > > > > > --- a/drivers/cxl/pci.c > > > > > > > +++ b/drivers/cxl/pci.c > > > > > > > @@ -428,11 +428,26 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) > > > > > > > } > > > > > > > } > > > > > > > > > > > > > > +static int check_restricted_device(struct pci_dev *pdev, u16 pcie_dvsec) > > > > > > > +{ > > > > > > > + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_END) > > > > > > > + return 0; /* no RCD */ > > > > > > > + > > > > > > > + if (pdev->devfn == PCI_DEVFN(0, 0) && pcie_dvsec) > > > > > > > + return 0; /* ok */ > > > > > > > + > > > > > > > + dev_warn(&pdev->dev, "Skipping RCD: devfn=0x%02x dvsec=%u\n", > > > > > > > > > > > > s/0x%02x/%#02x/ > > > > > > > > > > > > > + pdev->devfn, pcie_dvsec); > > > > > > > > > > Ok. > > > > > > > > > > > This looks like a dev_dbg() to me. Otherwise a warning will always fire > > > > > > on a benign condition. > > > > > > > > > > I have chosen dev_warn() here as this is a non-compliant unexpected > > > > > behavior of the device. There are no (legal) cases this may happen. I > > > > > suppose you are worried about spamming the console here, but that > > > > > error should be reported somewhere and thus being visible. > > > > > > > > There are so many spec illegal values and conditions that the driver > > > > could checki, but does not. The reason I am poking here is why does the > > > > driver need to be explicit about *this* illegal condition versus all the > > > > other potential conditions? What is the practical end user impact if > > > > Linux does not include this change? For example, if it is just one > > > > vendor that made this mistake that can be an explicit quirk. > > > > > > > > A dev_warn() is not necessary for simple quirks. > > > > > > This is not simply a cross check, the driver prevents enablement of > > > CXL mem devs other than PCI_DEVFN(0, 0). It shouldn't silently drop > > > out then. It's a device malfunction which should appropriate reported > > > and not only visible if dbg is enabled. > > > > > > As written above, the check is necessary as the counterpart is missing > > > > It is only necessary if this condition happens in practice, not a > > theoretically. So I am asking, are you seeing this with an actual device > > that someone will use in production? If so, that's what pci quirks are > > for to keep those workarounds organized in a common location. > > I can make it a dev_dbg() message. But I do not understand the ratio > behind this. This is not a quirk nor a workaround or a fix for > something. The likely paths are the conditions checked that return 0. > Only if the unlikely case happens where a CXL mem dev is not a dev 0, > func 0, a warning is shown to inform the user that this dev is not > enabled. So yes, this might be theoretical similar to that a driver > cannot allocate memory. But why not print this as a warning message > then? > > Anyway, let's make it a dev_dbg(). Sorry for the thrash, lets set aside the the dev_dbg() vs dev_warn() issue. It is minor compared to *why* this patch needs to be applied. I would expect all production devices to be spec compliant and not advertise the CXL memory device class code on anything but function0. So either, there is a real threat that someone will build such a mistake and Linux needs to take this action to protect itself, or no one will ever build such a device and this patch is not needed. Basically I read the changelog and it answered the "What?" question, but it did not answer the "Why?" question.
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index faeb5d9d7a7a..cc4f206f24b3 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -428,11 +428,26 @@ static void devm_cxl_pci_create_doe(struct cxl_dev_state *cxlds) } } +static int check_restricted_device(struct pci_dev *pdev, u16 pcie_dvsec) +{ + if (pci_pcie_type(pdev) != PCI_EXP_TYPE_RC_END) + return 0; /* no RCD */ + + if (pdev->devfn == PCI_DEVFN(0, 0) && pcie_dvsec) + return 0; /* ok */ + + dev_warn(&pdev->dev, "Skipping RCD: devfn=0x%02x dvsec=%u\n", + pdev->devfn, pcie_dvsec); + + return -ENODEV; +} + static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct cxl_register_map map; struct cxl_memdev *cxlmd; struct cxl_dev_state *cxlds; + u16 pcie_dvsec; int rc; /* @@ -442,6 +457,13 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) BUILD_BUG_ON(offsetof(struct cxl_regs, memdev) != offsetof(struct cxl_regs, device_regs.memdev)); + pcie_dvsec = pci_find_dvsec_capability( + pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + + rc = check_restricted_device(pdev, pcie_dvsec); + if (rc) + return rc; + rc = pcim_enable_device(pdev); if (rc) return rc; @@ -451,8 +473,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) return PTR_ERR(cxlds); cxlds->serial = pci_get_dsn(pdev); - cxlds->cxl_dvsec = pci_find_dvsec_capability( - pdev, PCI_DVSEC_VENDOR_ID_CXL, CXL_DVSEC_PCIE_DEVICE); + cxlds->cxl_dvsec = pcie_dvsec; if (!cxlds->cxl_dvsec) dev_warn(&pdev->dev, "Device DVSEC not present, skip CXL.mem init\n");
The Device 0, Function 0 DVSEC controls the CXL functionality of the entire device. Add a check to prevent registration of any other PCI device on the bus as a CXL memory device. Signed-off-by: Robert Richter <rrichter@amd.com> --- drivers/cxl/pci.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)