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Tue, 11 Apr 2023 18:04:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT114.mail.protection.outlook.com (10.13.177.46) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6298.28 via Frontend Transport; Tue, 11 Apr 2023 18:04:49 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 11 Apr 2023 13:04:48 -0500 From: Terry Bowman To: , , , , , , , CC: , , , , Oliver O'Halloran , Mahesh J Salgaonkar , , Subject: [PATCH v3 6/6] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Date: Tue, 11 Apr 2023 13:03:02 -0500 Message-ID: <20230411180302.2678736-7-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230411180302.2678736-1-terry.bowman@amd.com> References: <20230411180302.2678736-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT114:EE_|MN0PR12MB6032:EE_ X-MS-Office365-Filtering-Correlation-Id: ad78fed2-a404-40a9-905f-08db3ab73e0c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Apr 2023 18:04:49.6869 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad78fed2-a404-40a9-905f-08db3ab73e0c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT114.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6032 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Robert Richter RCEC AER corrected and uncorrectable internal errors (CIE/UIE) are disabled by default. [1][2] Enable them to receive CXL downstream port errors of a Restricted CXL Host (RCH). [1] CXL 3.0 Spec, 12.2.1.1 - RCH Downstream Port Detected Errors [2] PCIe Base Spec 6.0, 7.8.4.3 Uncorrectable Error Mask Register, 7.8.4.6 Correctable Error Mask Register Co-developed-by: Terry Bowman Signed-off-by: Robert Richter Signed-off-by: Terry Bowman Cc: "Oliver O'Halloran" Cc: Bjorn Helgaas Cc: Mahesh J Salgaonkar Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org --- drivers/pci/pcie/aer.c | 73 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 171a08fd8ebd..3973c731e11d 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -1000,7 +1000,79 @@ static void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) pcie_walk_rcec(dev, cxl_handle_error_iter, info); } +static bool cxl_error_is_native(struct pci_dev *dev) +{ + struct pci_host_bridge *host = pci_find_host_bridge(dev->bus); + + if (pcie_ports_native) + return true; + + return host->native_aer && host->native_cxl_error; +} + +static int handles_cxl_error_iter(struct pci_dev *dev, void *data) +{ + int *handles_cxl = data; + + *handles_cxl = is_cxl_mem_dev(dev) && cxl_error_is_native(dev); + + return *handles_cxl; +} + +static bool handles_cxl_errors(struct pci_dev *rcec) +{ + int handles_cxl = 0; + + if (!rcec->aer_cap) + return false; + + if (pci_pcie_type(rcec) == PCI_EXP_TYPE_RC_EC) + pcie_walk_rcec(rcec, handles_cxl_error_iter, &handles_cxl); + + return !!handles_cxl; +} + +static int __cxl_unmask_internal_errors(struct pci_dev *rcec) +{ + int aer, rc; + u32 mask; + + /* + * Internal errors are masked by default, unmask RCEC's here + * PCI6.0 7.8.4.3 Uncorrectable Error Mask Register (Offset 08h) + * PCI6.0 7.8.4.6 Correctable Error Mask Register (Offset 14h) + */ + aer = rcec->aer_cap; + rc = pci_read_config_dword(rcec, aer + PCI_ERR_UNCOR_MASK, &mask); + if (rc) + return rc; + mask &= ~PCI_ERR_UNC_INTN; + rc = pci_write_config_dword(rcec, aer + PCI_ERR_UNCOR_MASK, mask); + if (rc) + return rc; + + rc = pci_read_config_dword(rcec, aer + PCI_ERR_COR_MASK, &mask); + if (rc) + return rc; + mask &= ~PCI_ERR_COR_INTERNAL; + rc = pci_write_config_dword(rcec, aer + PCI_ERR_COR_MASK, mask); + + return rc; +} + +static void cxl_unmask_internal_errors(struct pci_dev *rcec) +{ + if (!handles_cxl_errors(rcec)) + return; + + if (__cxl_unmask_internal_errors(rcec)) + dev_err(&rcec->dev, "cxl: Failed to unmask internal errors"); + else + dev_dbg(&rcec->dev, "cxl: Internal errors unmasked"); +} + #else +static inline void cxl_unmask_internal_errors(struct pci_dev *dev) { } static inline void cxl_handle_error(struct pci_dev *dev, struct aer_err_info *info) { } #endif @@ -1397,6 +1469,7 @@ static int aer_probe(struct pcie_device *dev) return status; } + cxl_unmask_internal_errors(port); aer_enable_rootport(rpc); pci_info(port, "enabled with IRQ %d\n", dev->irq); return 0;