| Message ID | 20230607221651.2454764-14-terry.bowman@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cxl/pci: Add support for RCH RAS error handling | expand |
Terry Bowman wrote: > From: Robert Richter <rrichter@amd.com> > > Same as for ports, also store the downstream port's Component Register > mappings, use struct cxl_dport for that. > > Signed-off-by: Robert Richter <rrichter@amd.com> > Signed-off-by: Terry Bowman <terry.bowman@amd.com> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/core/port.c | 11 +++++++++++ > drivers/cxl/cxl.h | 2 ++ > 2 files changed, 13 insertions(+) > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 305125b193ce..a40d8cefb57d 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -708,6 +708,13 @@ static inline int cxl_port_setup_regs(struct cxl_port *port, > component_reg_phys); > } > > +static inline int cxl_dport_setup_regs(struct cxl_dport *dport, > + resource_size_t component_reg_phys) > +{ > + return cxl_setup_comp_regs(dport->dev, &dport->comp_map, > + component_reg_phys); > +} > + > static struct cxl_port *__devm_cxl_add_port(struct device *host, > struct device *uport, > resource_size_t component_reg_phys, > @@ -992,6 +999,10 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, > dport->component_reg_phys = component_reg_phys; > dport->port = port; > > + rc = cxl_dport_setup_regs(dport, component_reg_phys); > + if (rc && rc != -ENODEV) > + return ERR_PTR(rc); Ah I see that you wanted to share a similar function between this case and the last patch, but I would still remove one layer of indirection and make the setup return 0 if there is nothing to do rather than the if (rc && rc != -ENODEV) ...the stresses out the reader wondering where that special error code case is generated. Otherwise, makes sense.
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index 305125b193ce..a40d8cefb57d 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -708,6 +708,13 @@ static inline int cxl_port_setup_regs(struct cxl_port *port, component_reg_phys); } +static inline int cxl_dport_setup_regs(struct cxl_dport *dport, + resource_size_t component_reg_phys) +{ + return cxl_setup_comp_regs(dport->dev, &dport->comp_map, + component_reg_phys); +} + static struct cxl_port *__devm_cxl_add_port(struct device *host, struct device *uport, resource_size_t component_reg_phys, @@ -992,6 +999,10 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, dport->component_reg_phys = component_reg_phys; dport->port = port; + rc = cxl_dport_setup_regs(dport, component_reg_phys); + if (rc && rc != -ENODEV) + return ERR_PTR(rc); + cond_cxl_root_lock(port); rc = add_dport(port, dport); cond_cxl_root_unlock(port); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index c76e1f84ba61..dc83c1d0396e 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -601,6 +601,7 @@ struct cxl_rcrb_info { * struct cxl_dport - CXL downstream port * @dev: PCI bridge or firmware device representing the downstream link * @port: reference to cxl_port that contains this downstream port + * @comp_map: component register capability mappings * @port_id: unique hardware identifier for dport in decoder target list * @component_reg_phys: downstream port component registers * @rch: Indicate whether this dport was enumerated in RCH or VH mode @@ -609,6 +610,7 @@ struct cxl_rcrb_info { struct cxl_dport { struct device *dev; struct cxl_port *port; + struct cxl_register_map comp_map; int port_id; resource_size_t component_reg_phys; bool rch;