| Message ID | 20230622035126.4130151-12-terry.bowman@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cxl/pci: Add support for RCH RAS error handling | expand |
On 6/21/23 20:51, Terry Bowman wrote: > From: Robert Richter <rrichter@amd.com> > > The Component Register base address @component_reg_phys is no longer > used after the rework of the Component Register setup which now uses > struct member @comp_map instead. Remove the base address. > > Signed-off-by: Robert Richter <rrichter@amd.com> > Signed-off-by: Terry Bowman <terry.bowman@amd.com> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> > --- > drivers/cxl/core/port.c | 1 - > drivers/cxl/cxl.h | 2 -- > 2 files changed, 3 deletions(-) > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index cdfe0ea7a2e9..e0d2e7596440 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -960,7 +960,6 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, > > dport->dport_dev = dport_dev; > dport->port_id = port_id; > - dport->component_reg_phys = component_reg_phys; > dport->port = port; > > cond_cxl_root_lock(port); > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index ae265357170e..7fbc52b81554 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -594,7 +594,6 @@ struct cxl_rcrb_info { > * struct cxl_dport - CXL downstream port > * @dport_dev: PCI bridge or firmware device representing the downstream link > * @port_id: unique hardware identifier for dport in decoder target list > - * @component_reg_phys: downstream port component registers > * @rcrb: Data about the Root Complex Register Block layout > * @rch: Indicate whether this dport was enumerated in RCH or VH mode > * @port: reference to cxl_port that contains this downstream port > @@ -602,7 +601,6 @@ struct cxl_rcrb_info { > struct cxl_dport { > struct device *dport_dev; > int port_id; > - resource_size_t component_reg_phys; > struct cxl_rcrb_info rcrb; > bool rch; > struct cxl_port *port;
diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c index cdfe0ea7a2e9..e0d2e7596440 100644 --- a/drivers/cxl/core/port.c +++ b/drivers/cxl/core/port.c @@ -960,7 +960,6 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, dport->dport_dev = dport_dev; dport->port_id = port_id; - dport->component_reg_phys = component_reg_phys; dport->port = port; cond_cxl_root_lock(port); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index ae265357170e..7fbc52b81554 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -594,7 +594,6 @@ struct cxl_rcrb_info { * struct cxl_dport - CXL downstream port * @dport_dev: PCI bridge or firmware device representing the downstream link * @port_id: unique hardware identifier for dport in decoder target list - * @component_reg_phys: downstream port component registers * @rcrb: Data about the Root Complex Register Block layout * @rch: Indicate whether this dport was enumerated in RCH or VH mode * @port: reference to cxl_port that contains this downstream port @@ -602,7 +601,6 @@ struct cxl_rcrb_info { struct cxl_dport { struct device *dport_dev; int port_id; - resource_size_t component_reg_phys; struct cxl_rcrb_info rcrb; bool rch; struct cxl_port *port;