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Thu, 22 Jun 2023 03:54:55 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT030.mail.protection.outlook.com (10.13.177.146) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6500.41 via Frontend Transport; Thu, 22 Jun 2023 03:54:55 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 22:54:54 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v6 12/27] cxl/regs: Remove early capability checks in Component Register setup Date: Wed, 21 Jun 2023 22:51:11 -0500 Message-ID: <20230622035126.4130151-13-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622035126.4130151-1-terry.bowman@amd.com> References: <20230622035126.4130151-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT030:EE_|IA0PR12MB8747:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e69c060-30d2-4987-016d-08db72d470a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2023 03:54:55.0992 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e69c060-30d2-4987-016d-08db72d470a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT030.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8747 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Robert Richter When probing the Component Registers in function cxl_probe_regs() there are also checks for the existence of the HDM and RAS capabilities. The checks may fail for components that do not implement the HDM capability causing the Component Registers setup to fail too. Remove the checks for a generalized use of cxl_probe_regs() and check them directly before mapping the RAS or HDM capabilities. This allows it to setup other Component Registers esp. of an RCH Downstream Port, which will be implemented in a follow-on patch. Signed-off-by: Robert Richter Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang --- drivers/cxl/core/regs.c | 8 -------- drivers/cxl/pci.c | 2 ++ drivers/cxl/port.c | 5 ++++- 3 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index e035ad8827a4..e68848075bb6 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -369,14 +369,6 @@ static int cxl_probe_regs(struct cxl_register_map *map) case CXL_REGLOC_RBI_COMPONENT: comp_map = &map->component_map; cxl_probe_component_regs(dev, base, comp_map); - if (!comp_map->hdm_decoder.valid) { - dev_err(dev, "HDM decoder registers not found\n"); - return -ENXIO; - } - - if (!comp_map->ras.valid) - dev_dbg(dev, "RAS registers not found\n"); - dev_dbg(dev, "Set up component registers\n"); break; case CXL_REGLOC_RBI_MEMDEV: diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index ac17bc0430dc..945ca0304d68 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -630,6 +630,8 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); if (rc) dev_warn(&pdev->dev, "No component registers (%d)\n", rc); + else if (!map.component_map.ras.valid) + dev_dbg(&pdev->dev, "RAS registers not found\n"); cxlds->component_reg_phys = map.resource; diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 4cef2bf45ad2..01e84ea54f56 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -102,8 +102,11 @@ static int cxl_endpoint_port_probe(struct cxl_port *port) return rc; cxlhdm = devm_cxl_setup_hdm(port, &info); - if (IS_ERR(cxlhdm)) + if (IS_ERR(cxlhdm)) { + if (PTR_ERR(cxlhdm) == -ENODEV) + dev_err(&port->dev, "HDM decoder registers not found\n"); return PTR_ERR(cxlhdm); + } /* Cache the data early to ensure is_visible() works */ read_cdat_data(port);