| Message ID | 20230622035126.4130151-14-terry.bowman@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cxl/pci: Add support for RCH RAS error handling | expand |
On Wed, 21 Jun 2023 22:51:12 -0500 Terry Bowman <terry.bowman@amd.com> wrote: > From: Robert Richter <rrichter@amd.com> > > In order to move the RCH dport component register setup to cxl_pci the > base address must be stored in CXL device state (cxlds) for both > modes, RCH and VH. Store it in cxlds->component_reg_phys and use it > for endpoint creation. > > Signed-off-by: Robert Richter <rrichter@amd.com> > Signed-off-by: Terry Bowman <terry.bowman@amd.com> Seems reasonable. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > drivers/cxl/mem.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 4cc461c22b8b..7638a7f8f333 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -51,7 +51,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, > struct cxl_port *parent_port = parent_dport->port; > struct cxl_dev_state *cxlds = cxlmd->cxlds; > struct cxl_port *endpoint, *iter, *down; > - resource_size_t component_reg_phys; > int rc; > > /* > @@ -72,11 +71,11 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, > * typical register locator mechanism. > */ > if (parent_dport->rch && cxlds->component_reg_phys == CXL_RESOURCE_NONE) > - component_reg_phys = > + cxlds->component_reg_phys = > cxl_rcd_component_reg_phys(&cxlmd->dev, parent_dport); > - else > - component_reg_phys = cxlds->component_reg_phys; > - endpoint = devm_cxl_add_port(host, &cxlmd->dev, component_reg_phys, > + > + endpoint = devm_cxl_add_port(host, &cxlmd->dev, > + cxlds->component_reg_phys, > parent_dport); > if (IS_ERR(endpoint)) > return PTR_ERR(endpoint);
On 6/21/23 20:51, Terry Bowman wrote: > From: Robert Richter <rrichter@amd.com> > > In order to move the RCH dport component register setup to cxl_pci the > base address must be stored in CXL device state (cxlds) for both > modes, RCH and VH. Store it in cxlds->component_reg_phys and use it > for endpoint creation. > > Signed-off-by: Robert Richter <rrichter@amd.com> > Signed-off-by: Terry Bowman <terry.bowman@amd.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> > --- > drivers/cxl/mem.c | 9 ++++----- > 1 file changed, 4 insertions(+), 5 deletions(-) > > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 4cc461c22b8b..7638a7f8f333 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -51,7 +51,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, > struct cxl_port *parent_port = parent_dport->port; > struct cxl_dev_state *cxlds = cxlmd->cxlds; > struct cxl_port *endpoint, *iter, *down; > - resource_size_t component_reg_phys; > int rc; > > /* > @@ -72,11 +71,11 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, > * typical register locator mechanism. > */ > if (parent_dport->rch && cxlds->component_reg_phys == CXL_RESOURCE_NONE) > - component_reg_phys = > + cxlds->component_reg_phys = > cxl_rcd_component_reg_phys(&cxlmd->dev, parent_dport); > - else > - component_reg_phys = cxlds->component_reg_phys; > - endpoint = devm_cxl_add_port(host, &cxlmd->dev, component_reg_phys, > + > + endpoint = devm_cxl_add_port(host, &cxlmd->dev, > + cxlds->component_reg_phys, > parent_dport); > if (IS_ERR(endpoint)) > return PTR_ERR(endpoint);
diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 4cc461c22b8b..7638a7f8f333 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -51,7 +51,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, struct cxl_port *parent_port = parent_dport->port; struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_port *endpoint, *iter, *down; - resource_size_t component_reg_phys; int rc; /* @@ -72,11 +71,11 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, * typical register locator mechanism. */ if (parent_dport->rch && cxlds->component_reg_phys == CXL_RESOURCE_NONE) - component_reg_phys = + cxlds->component_reg_phys = cxl_rcd_component_reg_phys(&cxlmd->dev, parent_dport); - else - component_reg_phys = cxlds->component_reg_phys; - endpoint = devm_cxl_add_port(host, &cxlmd->dev, component_reg_phys, + + endpoint = devm_cxl_add_port(host, &cxlmd->dev, + cxlds->component_reg_phys, parent_dport); if (IS_ERR(endpoint)) return PTR_ERR(endpoint);