| Message ID | 20230622035126.4130151-18-terry.bowman@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cxl/pci: Add support for RCH RAS error handling | expand |
On 6/21/23 20:51, Terry Bowman wrote: > From: Robert Richter <rrichter@amd.com> > > Same as for ports and dports, also store the endpoint's Component > Register mappings, use struct cxl_dev_state for that. > > The Component Register base address @component_reg_phys is no longer > used after the rework of the Component Register setup which now uses > struct member @comp_map instead. Remove the base address. > > Signed-off-by: Robert Richter <rrichter@amd.com> > Signed-off-by: Terry Bowman <terry.bowman@amd.com> > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> > --- > drivers/cxl/cxlmem.h | 5 ++--- > drivers/cxl/mem.c | 4 ++-- > drivers/cxl/pci.c | 10 ++++------ > tools/testing/cxl/test/mem.c | 1 - > 4 files changed, 8 insertions(+), 12 deletions(-) > > diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h > index 76743016b64c..8aee1a42d9af 100644 > --- a/drivers/cxl/cxlmem.h > +++ b/drivers/cxl/cxlmem.h > @@ -263,6 +263,7 @@ struct cxl_poison_state { > * > * @dev: The device associated with this CXL state > * @cxlmd: The device representing the CXL.mem capabilities of @dev > + * @comp_map: component register capability mappings > * @regs: Parsed register blocks > * @cxl_dvsec: Offset to the PCIe device DVSEC > * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) > @@ -286,7 +287,6 @@ struct cxl_poison_state { > * @active_persistent_bytes: sum of hard + soft persistent > * @next_volatile_bytes: volatile capacity change pending device reset > * @next_persistent_bytes: persistent capacity change pending device reset > - * @component_reg_phys: register base of component registers > * @info: Cached DVSEC information about the device. > * @serial: PCIe Device Serial Number > * @event: event log driver state > @@ -299,7 +299,7 @@ struct cxl_poison_state { > struct cxl_dev_state { > struct device *dev; > struct cxl_memdev *cxlmd; > - > + struct cxl_register_map comp_map; > struct cxl_regs regs; > int cxl_dvsec; > > @@ -325,7 +325,6 @@ struct cxl_dev_state { > u64 next_volatile_bytes; > u64 next_persistent_bytes; > > - resource_size_t component_reg_phys; > u64 serial; > > struct cxl_event_state event; > diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c > index 205e2e280aed..92c6151b7206 100644 > --- a/drivers/cxl/mem.c > +++ b/drivers/cxl/mem.c > @@ -49,7 +49,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, > struct cxl_dport *parent_dport) > { > struct cxl_port *parent_port = parent_dport->port; > - struct cxl_dev_state *cxlds = cxlmd->cxlds; > struct cxl_port *endpoint, *iter, *down; > int rc; > > @@ -65,8 +64,9 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, > ep->next = down; > } > > + /* The Endpoint's component regs are located in cxlds. */ > endpoint = devm_cxl_add_port(host, &cxlmd->dev, > - cxlds->component_reg_phys, > + CXL_RESOURCE_NONE, > parent_dport); > if (IS_ERR(endpoint)) > return PTR_ERR(endpoint); > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index 99a75c54ee39..ad4cfcd95e17 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -665,16 +665,14 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) > * If the component registers can't be found, the cxl_pci driver may > * still be useful for management functions so don't return an error. > */ > - cxlds->component_reg_phys = CXL_RESOURCE_NONE; > - rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); > + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > + &cxlds->comp_map); > if (rc) > dev_warn(&pdev->dev, "No component registers (%d)\n", rc); > - else if (!map.component_map.ras.valid) > + else if (!cxlds->comp_map.component_map.ras.valid) > dev_dbg(&pdev->dev, "RAS registers not found\n"); > > - cxlds->component_reg_phys = map.resource; > - > - rc = cxl_map_component_regs(&map, &cxlds->regs.component, > + rc = cxl_map_component_regs(&cxlds->comp_map, &cxlds->regs.component, > BIT(CXL_CM_CAP_CAP_ID_RAS)); > if (rc) > dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); > diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c > index 34b48027b3de..fd562a5fa06f 100644 > --- a/tools/testing/cxl/test/mem.c > +++ b/tools/testing/cxl/test/mem.c > @@ -1241,7 +1241,6 @@ static int cxl_mock_mem_probe(struct platform_device *pdev) > cxlds->event.buf = (struct cxl_get_event_payload *) mdata->event_buf; > if (is_rcd(pdev)) { > cxlds->rcd = true; > - cxlds->component_reg_phys = CXL_RESOURCE_NONE; > } > > rc = cxl_enumerate_cmds(cxlds);
diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h index 76743016b64c..8aee1a42d9af 100644 --- a/drivers/cxl/cxlmem.h +++ b/drivers/cxl/cxlmem.h @@ -263,6 +263,7 @@ struct cxl_poison_state { * * @dev: The device associated with this CXL state * @cxlmd: The device representing the CXL.mem capabilities of @dev + * @comp_map: component register capability mappings * @regs: Parsed register blocks * @cxl_dvsec: Offset to the PCIe device DVSEC * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH) @@ -286,7 +287,6 @@ struct cxl_poison_state { * @active_persistent_bytes: sum of hard + soft persistent * @next_volatile_bytes: volatile capacity change pending device reset * @next_persistent_bytes: persistent capacity change pending device reset - * @component_reg_phys: register base of component registers * @info: Cached DVSEC information about the device. * @serial: PCIe Device Serial Number * @event: event log driver state @@ -299,7 +299,7 @@ struct cxl_poison_state { struct cxl_dev_state { struct device *dev; struct cxl_memdev *cxlmd; - + struct cxl_register_map comp_map; struct cxl_regs regs; int cxl_dvsec; @@ -325,7 +325,6 @@ struct cxl_dev_state { u64 next_volatile_bytes; u64 next_persistent_bytes; - resource_size_t component_reg_phys; u64 serial; struct cxl_event_state event; diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 205e2e280aed..92c6151b7206 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -49,7 +49,6 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, struct cxl_dport *parent_dport) { struct cxl_port *parent_port = parent_dport->port; - struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_port *endpoint, *iter, *down; int rc; @@ -65,8 +64,9 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, ep->next = down; } + /* The Endpoint's component regs are located in cxlds. */ endpoint = devm_cxl_add_port(host, &cxlmd->dev, - cxlds->component_reg_phys, + CXL_RESOURCE_NONE, parent_dport); if (IS_ERR(endpoint)) return PTR_ERR(endpoint); diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 99a75c54ee39..ad4cfcd95e17 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -665,16 +665,14 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) * If the component registers can't be found, the cxl_pci driver may * still be useful for management functions so don't return an error. */ - cxlds->component_reg_phys = CXL_RESOURCE_NONE; - rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map); + rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, + &cxlds->comp_map); if (rc) dev_warn(&pdev->dev, "No component registers (%d)\n", rc); - else if (!map.component_map.ras.valid) + else if (!cxlds->comp_map.component_map.ras.valid) dev_dbg(&pdev->dev, "RAS registers not found\n"); - cxlds->component_reg_phys = map.resource; - - rc = cxl_map_component_regs(&map, &cxlds->regs.component, + rc = cxl_map_component_regs(&cxlds->comp_map, &cxlds->regs.component, BIT(CXL_CM_CAP_CAP_ID_RAS)); if (rc) dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); diff --git a/tools/testing/cxl/test/mem.c b/tools/testing/cxl/test/mem.c index 34b48027b3de..fd562a5fa06f 100644 --- a/tools/testing/cxl/test/mem.c +++ b/tools/testing/cxl/test/mem.c @@ -1241,7 +1241,6 @@ static int cxl_mock_mem_probe(struct platform_device *pdev) cxlds->event.buf = (struct cxl_get_event_payload *) mdata->event_buf; if (is_rcd(pdev)) { cxlds->rcd = true; - cxlds->component_reg_phys = CXL_RESOURCE_NONE; } rc = cxl_enumerate_cmds(cxlds);