From patchwork Thu Jun 22 20:55:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13289840 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF5EDEB64DD for ; Thu, 22 Jun 2023 21:05:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229832AbjFVVFy (ORCPT ); Thu, 22 Jun 2023 17:05:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53420 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232068AbjFVVFA (ORCPT ); Thu, 22 Jun 2023 17:05:00 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on20610.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe59::610]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AA47421C; Thu, 22 Jun 2023 14:02:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hvGPzMYOyPiqtPld/Fk9CY0BmxbSu5IEpvaSswf/TTRxykUw5ewhwV4MlFept77RQYsrUCwVhM8qveYejj5vnHEubfSNdeOAjVIJeeC3VgADDwDhdEoMtpIuXM3D+DaASfgOwJSx8S2/Q4ejmhyYnCIG2TyOeJK76g2XbjoPJIMlFsrF+LXwthX3eZxkAEu8x8e0rjz8GmGgUCmmzmSjLp0xO16yGhsys/JRpMLTq2BLjU7KhhP238o1NAkd9pypIIAlvjmr6WAgiN0TOSWyM3a+oHIoVnb1M7mkrphSI7+B9fNgW5Q33wkpg2V589pGk2zfkuWqFrt0sJhEdB1vdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zJGb8iVAmjFWLMxEIW//gmwKAZ4/XIlDRXWXqsX637M=; b=EkaXsCPWK3GK6jrjkRrKd1zhP9wRgFv3LJoruEqE6QtIvnqojW54lcUDIT+9mVt5mKCOYQ2aZAVSyJM4WgB82+LqymK5SiJcfqEZq1/cL/e4/8By0TGWixbBWd2wYRX+XsMhpfJ6eJM2Di1nOTIaWulZluCct33fbHjlFwsnA9/Jvb98p/e7vqDULjJU7VJpSTPPkkqEMmKg+MUAnZksmJ4t22uozJqL4B9c1LJ4KxNz2oTDWlO1gs5RMinqUQJW8Iq0EGxdWbr+iKrgIMTPtSY73CzHerAvmI9UQF4YbNjtpvi6MGOb51FEQJ2Zn70ABzryyUFIS5dqjjXiSygoMA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=intel.com smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zJGb8iVAmjFWLMxEIW//gmwKAZ4/XIlDRXWXqsX637M=; b=ZHLCrw3Rn+pTinhKT/NV4rFILMh9fcrj/qgbdwht8pezBHBYrr5B8+IMxgP1wHFueW9IDDz7nyGmYx/4KQRVFEO9XU1Ica6uXcM4JJFProoIp1fy/4qQh8UbcPBn3woQShwZicFIXKMu9ZAbyEnD9pv2aj825ditBQvlDnwSSfY= Received: from CY5PR15CA0147.namprd15.prod.outlook.com (2603:10b6:930:67::16) by SJ2PR12MB8783.namprd12.prod.outlook.com (2603:10b6:a03:4d0::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.24; Thu, 22 Jun 2023 20:59:24 +0000 Received: from CY4PEPF0000EE34.namprd05.prod.outlook.com (2603:10b6:930:67:cafe::b6) by CY5PR15CA0147.outlook.office365.com (2603:10b6:930:67::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6521.24 via Frontend Transport; Thu, 22 Jun 2023 20:59:24 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE34.mail.protection.outlook.com (10.167.242.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.17 via Frontend Transport; Thu, 22 Jun 2023 20:59:23 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Thu, 22 Jun 2023 15:59:23 -0500 From: Terry Bowman To: , , , , , , , CC: , , , Subject: [PATCH v7 21/27] cxl/pci: Update CXL error logging to use RAS register address Date: Thu, 22 Jun 2023 15:55:17 -0500 Message-ID: <20230622205523.85375-22-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230622205523.85375-1-terry.bowman@amd.com> References: <20230622205523.85375-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE34:EE_|SJ2PR12MB8783:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e8119bd-9187-4163-1e64-08db73638ef7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XQiQD0WY2Son8Cb0afoH+7cpVL4CdPRRogKWELiRMp60La8iKIKfwpVH/Nz93iAe7MJLzUMYffalboVEt7yG5nfC7sTvnLW4jiZaR7vVxmc0jDkydMYWKbv9TW8Jp75Jay5yQQzjoHk+VGXfS6aRtDzdvJo9xBHfTQslHsHkRZYxNrH0Q/up08K4y8xZqxrqQxCw9HBYfvV0rMQgxd9poPrvqSByV2xfOloiNtqai5I+G8s7mx0hnkfSgoHrPmH/kK2t3eE6ZFWJ1c6kWuRUSvN3Nkk66u85s2YQfVe1aFUZ1MLFYXhJYqv5U93jEztTpoR2YH7JOadU8/GwylRHAVBRaj1g6NEl3vBbwg56GuR7DHR6klxdj6Jss6UTnzIKiDfcIeETgOlNgX0WJCG0FlKB1vVocc2hQ8MPHoXLAp8hSZLjeQ6PHBdM6v4Dl41Vb9JlzAqT2WtOzRDqdDBBFwTKbE/wE0L1znCpRe2ZE+/llH94uQBjW5nJYUD1lDhV0XnIRsbp7U1M2/xxcO3Ri22+dKp5IohfBz6x65NmqlHN5CkDf5LAOmMPTeYzyhqbpjeTmtruKqawRIPH3x3OqivctE43vs95vh2kxBvx8WPOpqIlCbCp4f4vVK2Fpm/+ifG7y8eM9P6opvJj/M0obY8nFXdfdVtDCUJPckvaA/mjD2sEib5JpfjIwTEVz7in+z3pIKkFyeq6/KD4EbvSvC3J3Jwq8MF9gRHaIoX2V8TnT34ivj37iAMfnn4BhfnptkikADcNX2Q9jm7vgfOscA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230028)(4636009)(136003)(346002)(39860400002)(396003)(376002)(451199021)(46966006)(36840700001)(40470700004)(82310400005)(40480700001)(40460700003)(86362001)(47076005)(8676002)(336012)(70586007)(70206006)(2616005)(316002)(44832011)(15650500001)(83380400001)(8936002)(41300700001)(7416002)(5660300002)(7696005)(1076003)(426003)(478600001)(6666004)(4326008)(186003)(16526019)(26005)(54906003)(110136005)(82740400003)(356005)(81166007)(36860700001)(2906002)(36756003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jun 2023 20:59:23.9479 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e8119bd-9187-4163-1e64-08db73638ef7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE34.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8783 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The CXL error handler currently only logs endpoint RAS status. The CXL topology includes several components providing RAS details to be logged during error handling.[1] Update the current handler's RAS logging to use a RAS register address. Also, update the error handler function names to be consistent with correctable and uncorrecable RAS. This will allow for adding support to log other CXL component's RAS details in the future. [1] CXL3.0 Table 8-22 CXL_Capability_ID Assignment Co-developed-by: Robert Richter Signed-off-by: Robert Richter Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang --- drivers/cxl/core/pci.c | 44 +++++++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 13 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 375f01c6cad6..9cb39835e154 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -665,32 +665,36 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL); -void cxl_cor_error_detected(struct pci_dev *pdev) +static void __cxl_handle_cor_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { - struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); void __iomem *addr; u32 status; - if (!cxlds->regs.ras) + if (!ras_base) return; - addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_STATUS_OFFSET; + addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status = readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); trace_cxl_aer_correctable_error(cxlds->cxlmd, status); } } -EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL); + +static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) +{ + return __cxl_handle_cor_ras(cxlds, cxlds->regs.ras); +} /* CXL spec rev3.0 8.2.4.16.1 */ -static void header_log_copy(struct cxl_dev_state *cxlds, u32 *log) +static void header_log_copy(void __iomem *ras_base, u32 *log) { void __iomem *addr; u32 *log_addr; int i, log_u32_size = CXL_HEADERLOG_SIZE / sizeof(u32); - addr = cxlds->regs.ras + CXL_RAS_HEADER_LOG_OFFSET; + addr = ras_base + CXL_RAS_HEADER_LOG_OFFSET; log_addr = log; for (i = 0; i < log_u32_size; i++) { @@ -704,17 +708,18 @@ static void header_log_copy(struct cxl_dev_state *cxlds, u32 *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool cxl_report_and_clear(struct cxl_dev_state *cxlds) +static bool __cxl_handle_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; u32 status; u32 fe; - if (!cxlds->regs.ras) + if (!ras_base) return false; - addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; + addr = ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status = readl(addr); if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) return false; @@ -722,7 +727,7 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds) /* If multiple errors, log header points to first error from ctrl reg */ if (hweight32(status) > 1) { void __iomem *rcc_addr = - cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET; + ras_base + CXL_RAS_CAP_CONTROL_OFFSET; fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(rcc_addr))); @@ -730,13 +735,26 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds) fe = status; } - header_log_copy(cxlds, hl); + header_log_copy(ras_base, hl); trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); return true; } +static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds) +{ + return __cxl_handle_ras(cxlds, cxlds->regs.ras); +} + +void cxl_cor_error_detected(struct pci_dev *pdev) +{ + struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); + + cxl_handle_endpoint_cor_ras(cxlds); +} +EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL); + pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { @@ -751,7 +769,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, * chance the situation is recoverable dump the status of the RAS * capability registers and bounce the active state of the memdev. */ - ue = cxl_report_and_clear(cxlds); + ue = cxl_handle_endpoint_ras(cxlds); switch (state) { case pci_channel_io_normal: