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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jul 2023 19:23:27.9250 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b33d5df1-9777-4e15-1e40-08db888da14a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT023.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4364 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org According to Section 9.17.2, Table 9-26 of CXL Specification [1], owner of AER should also own CXL Protocol Error Management as there is no explicit control of CXL Protocol error. And the CXL RAS Cap registers reported on Protocol errors should check for AER _OSC rather than CXL Memory Error Reporting Control _OSC. The CXL Memory Error Reporting Control _OSC specifically highlights handling Memory Error Logging and Signaling Enhancements. These kinds of errors are reported through a device's mailbox and can be managed independently from CXL Protocol Errors. [1] Compute Express Link (CXL) Specification, Revision 3.1, Aug 1 2022. Signed-off-by: Smita Koralahalli --- drivers/cxl/pci.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 1cb1494c28fe..44a21ab7add5 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, static int cxl_pci_ras_unmask(struct pci_dev *pdev) { - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); void __iomem *addr; u32 orig_val, val, mask; @@ -541,9 +540,9 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) return 0; } - /* BIOS has CXL error control */ - if (!host_bridge->native_cxl_error) - return -ENXIO; + /* BIOS has PCIe AER error control */ + if (!pcie_aer_is_native(pdev)) + return 0; rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); if (rc)