| Message ID | 20230925161124.18940-6-Jonathan.Cameron@huawei.com |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU: CXL mailbox rework and features | expand |
On Mon, Sep 25, 2023 at 05:11:10PM +0100, Jonathan Cameron wrote: > To avoid repetition of switch upstream port specific data in the > CXLDeviceState structure it will be necessary to access the switch USP > specific data from mailbox callbacks. Hence move it to cxl_device.h so it > is no longer an opaque structure. > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- Reviewed-by: Fan Ni <fan.ni@samsung.com> > include/hw/pci-bridge/cxl_upstream_port.h | 18 ++++++++++++++++++ > hw/pci-bridge/cxl_upstream.c | 11 +---------- > 2 files changed, 19 insertions(+), 10 deletions(-) > > diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bridge/cxl_upstream_port.h > new file mode 100644 > index 0000000000..b02aa8f659 > --- /dev/null > +++ b/include/hw/pci-bridge/cxl_upstream_port.h > @@ -0,0 +1,18 @@ > + > +#ifndef CXL_USP_H > +#define CXL_USP_H > +#include "hw/pci/pcie.h" > +#include "hw/pci/pcie_port.h" > +#include "hw/cxl/cxl.h" > + > +typedef struct CXLUpstreamPort { > + /*< private >*/ > + PCIEPort parent_obj; > + > + /*< public >*/ > + CXLComponentState cxl_cstate; > + DOECap doe_cdat; > + uint64_t sn; > +} CXLUpstreamPort; > + > +#endif /* CXL_SUP_H */ > diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c > index b81bb5fec9..36737189c6 100644 > --- a/hw/pci-bridge/cxl_upstream.c > +++ b/hw/pci-bridge/cxl_upstream.c > @@ -14,6 +14,7 @@ > #include "hw/pci/msi.h" > #include "hw/pci/pcie.h" > #include "hw/pci/pcie_port.h" > +#include "hw/pci-bridge/cxl_upstream_port.h" > /* > * Null value of all Fs suggested by IEEE RA guidelines for use of > * EU, OUI and CID > @@ -30,16 +31,6 @@ > #define CXL_UPSTREAM_PORT_DVSEC_OFFSET \ > (CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF) > > -typedef struct CXLUpstreamPort { > - /*< private >*/ > - PCIEPort parent_obj; > - > - /*< public >*/ > - CXLComponentState cxl_cstate; > - DOECap doe_cdat; > - uint64_t sn; > -} CXLUpstreamPort; > - > CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp) > { > return &usp->cxl_cstate; > -- > 2.39.2 >
diff --git a/include/hw/pci-bridge/cxl_upstream_port.h b/include/hw/pci-bridge/cxl_upstream_port.h new file mode 100644 index 0000000000..b02aa8f659 --- /dev/null +++ b/include/hw/pci-bridge/cxl_upstream_port.h @@ -0,0 +1,18 @@ + +#ifndef CXL_USP_H +#define CXL_USP_H +#include "hw/pci/pcie.h" +#include "hw/pci/pcie_port.h" +#include "hw/cxl/cxl.h" + +typedef struct CXLUpstreamPort { + /*< private >*/ + PCIEPort parent_obj; + + /*< public >*/ + CXLComponentState cxl_cstate; + DOECap doe_cdat; + uint64_t sn; +} CXLUpstreamPort; + +#endif /* CXL_SUP_H */ diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index b81bb5fec9..36737189c6 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -14,6 +14,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" +#include "hw/pci-bridge/cxl_upstream_port.h" /* * Null value of all Fs suggested by IEEE RA guidelines for use of * EU, OUI and CID @@ -30,16 +31,6 @@ #define CXL_UPSTREAM_PORT_DVSEC_OFFSET \ (CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF) -typedef struct CXLUpstreamPort { - /*< private >*/ - PCIEPort parent_obj; - - /*< public >*/ - CXLComponentState cxl_cstate; - DOECap doe_cdat; - uint64_t sn; -} CXLUpstreamPort; - CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp) { return &usp->cxl_cstate;
To avoid repetition of switch upstream port specific data in the CXLDeviceState structure it will be necessary to access the switch USP specific data from mailbox callbacks. Hence move it to cxl_device.h so it is no longer an opaque structure. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- include/hw/pci-bridge/cxl_upstream_port.h | 18 ++++++++++++++++++ hw/pci-bridge/cxl_upstream.c | 11 +---------- 2 files changed, 19 insertions(+), 10 deletions(-)