From patchwork Fri Jan 26 12:16:34 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 13532524 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B936114298 for ; Fri, 26 Jan 2024 12:18:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706271490; cv=none; b=GdNGW8qR+d5wDncHUNSVNVWlW8T807WkOmlpvGDxHkl1FosK0L1uY+ztfHY3ciLu2epwav6g1I4IVYXOrnod5Q20nt455nQG4J3DBfULxUke7UKJtZAW9N1AHbI+alm58G54f8bwjC+S7SQga8f92v9HbTjg7xv9TCEzraYnq/Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706271490; c=relaxed/simple; bh=myp3wD2scjP8+98vRAmimJ3ZwR7e1y/S0YbulptSLqw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=PBkIQB4rdm4Ks5ex5AB5/KGVd4ZQkehfjvrqr6vCFYOeBLf1y57yxMOpgzAE0oAlCQzKXFlEp182mKaOazUiF0CvM7fNo5fNdDjNQzie/CXBWcJHDX/6U61AN7g+o5d7sZwi9f0mRdi0ot24jce7J7vyWXnRKJQrqPMIRmdj6m0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.231]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4TLxTk6FRkz6K8j7; Fri, 26 Jan 2024 20:15:06 +0800 (CST) Received: from lhrpeml500005.china.huawei.com (unknown [7.191.163.240]) by mail.maildlp.com (Postfix) with ESMTPS id 50B6C140AB8; Fri, 26 Jan 2024 20:18:06 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Fri, 26 Jan 2024 12:18:05 +0000 From: Jonathan Cameron To: , , Fan Ni , Michael Tsirkin CC: Davidlohr Bueso , , =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 3/5] hw/cxl: Update RAS Capability Definitions for version 3. Date: Fri, 26 Jan 2024 12:16:34 +0000 Message-ID: <20240126121636.24611-4-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240126121636.24611-1-Jonathan.Cameron@huawei.com> References: <20240126121636.24611-1-Jonathan.Cameron@huawei.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: lhrpeml500006.china.huawei.com (7.191.161.198) To lhrpeml500005.china.huawei.com (7.191.163.240) Part of bringing all of CXL emulation inline with CXL r3.1. No functional changes. Reviewed-by: Fan Ni Signed-off-by: Jonathan Cameron --- include/hw/cxl/cxl_component.h | 5 ++++- hw/cxl/cxl-component-utils.c | 2 +- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 2c7631bd1e..b5da72b789 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -60,8 +60,9 @@ CXLx_CAPABILITY_HEADER(SNOOP, 0x14) * implements. Some of these are specific to certain types of components, but * this implementation leaves enough space regardless. */ -/* 8.2.5.9 - CXL RAS Capability Structure */ +/* CXL r3.1 Section 8.2.4.17: CXL RAS Capability Structure */ +#define CXL_RAS_CAPABILITY_VERSION 3 /* Give ample space for caps before this */ #define CXL_RAS_REGISTERS_OFFSET 0x80 #define CXL_RAS_REGISTERS_SIZE 0x58 @@ -95,6 +96,8 @@ REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc) REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10) REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14) FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6) + FIELD(CXL_RAS_ERR_CAP_CTRL, MULTIPLE_HEADER_RECORDING_CAP, 9, 1) + FIELD(CXL_RAS_ERR_POISON_ENABLED, POISON_ENABLED, 13, 1) REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18) #define CXL_RAS_ERR_HEADER_NUM 32 /* Offset 0x18 - 0x58 reserved for RAS logs */ diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c index a55cf5a036..848bfa20f1 100644 --- a/hw/cxl/cxl-component-utils.c +++ b/hw/cxl/cxl-component-utils.c @@ -325,7 +325,7 @@ void cxl_component_register_init_common(uint32_t *reg_state, CXL_##reg##_REGISTERS_OFFSET); \ } while (0) - init_cap_reg(RAS, 2, 2); + init_cap_reg(RAS, 2, CXL_RAS_CAPABILITY_VERSION); ras_init_common(reg_state, write_msk); init_cap_reg(LINK, 4, 2);