From patchwork Wed Jan 31 16:25:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mathieu Desnoyers X-Patchwork-Id: 13539655 Received: from smtpout.efficios.com (smtpout.efficios.com [167.114.26.122]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 897E312BE9D; Wed, 31 Jan 2024 16:25:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=167.114.26.122 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706718352; cv=none; b=V0C4vzYYDvTcysYeIH+t4j+GElvPSilRboIKrlapuMkcOKdOFa2eWxBt1RgsIj1cnLKS1F9DgtWrmTCwhnvePz2mtnGsvkj8Z1JIlYGjC/unPKicKeseS63u9DDaKjjePkInN36UMsfhPt2b28TH12itQtzRcur5ug4XPCcBsik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706718352; c=relaxed/simple; bh=eX0TXo9pcQzgnT4JpiJ1uz+KvY1x3UAQjUEMAJVLHgE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=p7wK+DcVP7CkWGWEBI3hBtwHsbaYLW/8n/E8wsVehJ3B0czv+slQ+9N8/SUE5sVRiBD0Lsj6Mq0P+dmAwSPcDrNS/DlwxnNbDOAK5I6PiZmdS95P/lmnDDsa0CKqmvJrHSXrxseRDdzMGH8F/FOUUPQpuJOxgEhQ9T/r+DotJgs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=efficios.com; spf=pass smtp.mailfrom=efficios.com; dkim=pass (2048-bit key) header.d=efficios.com header.i=@efficios.com header.b=HA2Zt+xx; arc=none smtp.client-ip=167.114.26.122 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=efficios.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=efficios.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=efficios.com header.i=@efficios.com header.b="HA2Zt+xx" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=efficios.com; s=smtpout1; t=1706718349; bh=eX0TXo9pcQzgnT4JpiJ1uz+KvY1x3UAQjUEMAJVLHgE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HA2Zt+xxhsvOb4O2UchDtcajfJ8ji+gNYMyIjAGZ5EQWJYleafh08/eminp77aE82 yajKp/NCmwT9QgTnvK/lTjgc7JIeNPSy8OUEcPFCHvxToJXJOl1x+D89IDEw3SnePY HGYVNr8qWrGj0nxbnfdG/h4ky03ZNKXxoNWxV0+YPw/t1zr8gq/bQQlqqJb50gIUWj lAj2UWcRkVhbWaTg+78o35p3+S3Ghr9Cg2Ii6UU64XHEvV7/avptbzfMDDiPYGDOD+ vFw7mg9tqqdM9u0smvoSSRwh4/CSG1XgucTAvwWj3hKokxfqG7+Q+wSjDRNZ6qGj4w HNu4r51PyvvHw== Received: from thinkos.internal.efficios.com (192-222-143-198.qc.cable.ebox.net [192.222.143.198]) by smtpout.efficios.com (Postfix) with ESMTPSA id 4TQ6pj2GjXzVp1; Wed, 31 Jan 2024 11:25:49 -0500 (EST) From: Mathieu Desnoyers To: Dan Williams , Arnd Bergmann , Dave Chinner Cc: linux-kernel@vger.kernel.org, Mathieu Desnoyers , Andrew Morton , Linus Torvalds , linux-mm@kvack.org, linux-arch@vger.kernel.org, Vishal Verma , Dave Jiang , Matthew Wilcox , Russell King , nvdimm@lists.linux.dev, linux-cxl@vger.kernel.org, linux-fsdevel@vger.kernel.org, dm-devel@lists.linux.dev Subject: [RFC PATCH v3 4/4] dax: Fix incorrect list of data cache aliasing architectures Date: Wed, 31 Jan 2024 11:25:33 -0500 Message-Id: <20240131162533.247710-5-mathieu.desnoyers@efficios.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240131162533.247710-1-mathieu.desnoyers@efficios.com> References: <20240131162533.247710-1-mathieu.desnoyers@efficios.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 commit d92576f1167c ("dax: does not work correctly with virtual aliasing caches") prevents DAX from building on architectures with virtually aliased dcache with: depends on !(ARM || MIPS || SPARC) This check is too broad (e.g. recent ARMv7 don't have virtually aliased dcaches), and also misses many other architectures with virtually aliased data cache. This is a regression introduced in the v5.13 Linux kernel where the dax mount option is removed for 32-bit ARMv7 boards which have no data cache aliasing, and therefore should work fine with FS_DAX. This was turned into the following check in alloc_dax() by a preparatory change: if (IS_ENABLED(CONFIG_ARM) || IS_ENABLED(CONFIG_MIPS) || IS_ENABLED(CONFIG_SPARC)) return NULL; Use cpu_dcache_is_aliasing() instead to figure out whether the environment has aliasing data caches. Fixes: d92576f1167c ("dax: does not work correctly with virtual aliasing caches") Signed-off-by: Mathieu Desnoyers Cc: Andrew Morton Cc: Linus Torvalds Cc: linux-mm@kvack.org Cc: linux-arch@vger.kernel.org Cc: Dan Williams Cc: Vishal Verma Cc: Dave Jiang Cc: Matthew Wilcox Cc: Arnd Bergmann Cc: Russell King Cc: nvdimm@lists.linux.dev Cc: linux-cxl@vger.kernel.org Cc: linux-fsdevel@vger.kernel.org Cc: dm-devel@lists.linux.dev --- drivers/dax/super.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/dax/super.c b/drivers/dax/super.c index e9f397b8a5a3..8c3a6e8e6334 100644 --- a/drivers/dax/super.c +++ b/drivers/dax/super.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "dax-private.h" /** @@ -446,9 +447,7 @@ struct dax_device *alloc_dax(void *private, const struct dax_operations *ops) int minor; /* Unavailable on architectures with virtually aliased data caches. */ - if (IS_ENABLED(CONFIG_ARM) || - IS_ENABLED(CONFIG_MIPS) || - IS_ENABLED(CONFIG_SPARC)) + if (cpu_dcache_is_aliasing()) return NULL; if (WARN_ON_ONCE(ops && !ops->zero_page_range))