diff mbox series

[RFC,09/11] cxl/ras: Set registers to sensible state for FW first ras

Message ID 20240205141940.31111-10-Jonathan.Cameron@huawei.com
State New, archived
Headers show
Series arm/acpi/pci/cxl: ACPI based FW First error injection. | expand

Commit Message

Jonathan Cameron Feb. 5, 2024, 2:19 p.m. UTC 
Even if we are doing native RAS, until the point where the OS
requests it via an _OSC the firmware may well be handling any
errors from CXL devices.  As such configure them as if a firmware
has been doing so.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 hw/cxl/cxl-component-utils.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
diff mbox series

Patch

diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index a0ff7d4396..e869c482a7 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -217,13 +217,13 @@  static void ras_init_common(uint32_t *reg_state, uint32_t *write_msk)
     stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_STATUS, 0);
     stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_STATUS, 0x1cfff);
     /* Bits 12-13 and 17-31 reserved in CXL 2.0 */
-    stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
+    stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_MASK, 0/*0x1cfff*/);
     stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_MASK, 0x1cfff);
     stl_le_p(reg_state + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
     stl_le_p(write_msk + R_CXL_RAS_UNC_ERR_SEVERITY, 0x1cfff);
     stl_le_p(reg_state + R_CXL_RAS_COR_ERR_STATUS, 0);
     stl_le_p(write_msk + R_CXL_RAS_COR_ERR_STATUS, 0x7f);
-    stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0x7f);
+    stl_le_p(reg_state + R_CXL_RAS_COR_ERR_MASK, 0/*0x7f*/);
     stl_le_p(write_msk + R_CXL_RAS_COR_ERR_MASK, 0x7f);
     /* CXL switches and devices must set */
     stl_le_p(reg_state + R_CXL_RAS_ERR_CAP_CTRL, 0x200);