[RFC,02/11] hw/acpi: Allow GPEX _OSC to keep fw first control of AER and CXL errors.

Message ID	20240205141940.31111-3-Jonathan.Cameron@huawei.com
State	New, archived
Headers	show Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5CDFD2421C for <linux-cxl@vger.kernel.org>; Mon, 5 Feb 2024 14:20:40 +0000 (UTC) From: Jonathan Cameron <Jonathan.Cameron@huawei.com> To: <linux-cxl@vger.kernel.org>, <qemu-devel@nongnu.org> CC: Igor Mammedov <imammedo@redhat.com>, Ani Sinha <anisinha@redhat.com>, Shannon Zhao <shannon.zhaosl@gmail.com>, Dongjiu Geng <gengdongjiu1@gmail.com>, <linuxarm@huawei.com>, "Michael S . Tsirkin" <mst@redhat.com>, Ira Weiny <ira.weiny@intel.com>, Peter Maydell <peter.maydell@linaro.org>, Fan Ni <fan.ni@samsung.com>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Subject: [RFC PATCH 02/11] hw/acpi: Allow GPEX _OSC to keep fw first control of AER and CXL errors. Date: Mon, 5 Feb 2024 14:19:31 +0000 Message-ID: <20240205141940.31111-3-Jonathan.Cameron@huawei.com> In-Reply-To: <20240205141940.31111-1-Jonathan.Cameron@huawei.com> References: <20240205141940.31111-1-Jonathan.Cameron@huawei.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain
Series	arm/acpi/pci/cxl: ACPI based FW First error injection. \| expand [RFC,00/11,qemu] arm/acpi/pci/cxl: ACPI based FW First error injection. [RFC,01/11] hw/pci: Add pcie_find_dvsec() utility. [RFC,02/11] hw/acpi: Allow GPEX _OSC to keep fw first control of AER and CXL errors. [RFC,03/11] arm/virt: Add fw-first-ras property. [RFC,04/11] acpi/ghes: Support GPIO error source. [RFC,05/11] arm/virt: Wire up GPIO error source for ACPI / GHES [RFC,06/11] acpi: pci/cxl: Stash the OSC control parameters. [RFC,07/11] pci/aer: Support firmware first error injection via GHESv2 [RFC,08/11] hw/pci/aer: Default to error handling on. [RFC,09/11] cxl/ras: Set registers to sensible state for FW first ras [RFC,10/11] cxl/type3: FW first protocol error injection. [RFC,11/11] cxl/type3: Add firmware first error reporting for general media events.

diff --git a/include/hw/acpi/cxl.h b/include/hw/acpi/cxl.h index 8f22c71530..38714147ec 100644 --- a/include/hw/acpi/cxl.h +++ b/include/hw/acpi/cxl.h @@ -24,7 +24,7 @@ void cxl_build_cedt(GArray *table_offsets, GArray *table_data, BIOSLinker *linker, const char *oem_id, const char *oem_table_id, CXLState *cxl_state); -void build_cxl_osc_method(Aml *dev); +void build_cxl_osc_method(Aml *dev, bool fw_first); void build_cxl_dsm_method(Aml *dev); #endif diff --git a/include/hw/pci-host/gpex.h b/include/hw/pci-host/gpex.h index dce883573b..866ae71ba0 100644 --- a/include/hw/pci-host/gpex.h +++ b/include/hw/pci-host/gpex.h @@ -47,6 +47,7 @@ struct GPEXConfig { MemMapEntry pio; int irq; PCIBus *bus; + bool fw_first_ras; }; struct GPEXHost { diff --git a/hw/acpi/cxl-stub.c b/hw/acpi/cxl-stub.c index 15bc21076b..0ec5c48850 100644 --- a/hw/acpi/cxl-stub.c +++ b/hw/acpi/cxl-stub.c @@ -6,7 +6,7 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/cxl.h" -void build_cxl_osc_method(Aml *dev) +void build_cxl_osc_method(Aml *dev, bool fw_first) { g_assert_not_reached(); } diff --git a/hw/acpi/cxl.c b/hw/acpi/cxl.c index d0e6a4b45e..526cfe961a 100644 --- a/hw/acpi/cxl.c +++ b/hw/acpi/cxl.c @@ -27,6 +27,7 @@ #include "hw/acpi/aml-build.h" #include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/cxl.h" +#include "hw/acpi/ghes.h" #include "qapi/error.h" #include "qemu/uuid.h" @@ -222,11 +223,12 @@ void cxl_build_cedt(GArray *table_offsets, GArray *table_data, acpi_table_end(linker, &table); } -static Aml *__build_cxl_osc_method(void) +static Aml *__build_cxl_osc_method(bool fw_first) { Aml *method, *if_uuid, *else_uuid, *if_arg1_not_1, *if_cxl, *if_caps_masked; Aml *a_ctrl = aml_local(0); Aml *a_cdw1 = aml_name("CDW1"); + Aml *cxl_ctrl = aml_local(2); method = aml_method("_OSC", 4, AML_NOTSERIALIZED); /* CDW1 is used for the return value so is present whether or not a match occurs */ @@ -260,7 +262,11 @@ static Aml *__build_cxl_osc_method(void) * Allows OS control for all 5 features: * PCIeHotplug SHPCHotplug PME AER PCIeCapability */ - aml_append(if_uuid, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); + if (fw_first) { + aml_append(if_uuid, aml_and(a_ctrl, aml_int(0x17), a_ctrl)); + } else { + aml_append(if_uuid, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); + } /* * Check _OSC revision. @@ -290,6 +296,23 @@ static Aml *__build_cxl_osc_method(void) aml_append(if_cxl, aml_create_dword_field(aml_arg(3), aml_int(12), "CDW4")); /* CXL capabilities */ aml_append(if_cxl, aml_create_dword_field(aml_arg(3), aml_int(16), "CDW5")); + + aml_append(if_cxl, aml_store(aml_name("CDW5"), cxl_ctrl)); + if (fw_first) { + aml_append(if_cxl, aml_and(cxl_ctrl, aml_int(0x0), cxl_ctrl)); + } else { + /* Only allow CXL Memory Error Reporting */ + aml_append(if_cxl, aml_and(cxl_ctrl, aml_int(0x1), cxl_ctrl)); + } + + if_caps_masked = aml_if(aml_lnot(aml_equal(aml_name("CDW5"), cxl_ctrl))); + + /* Capability bits were masked */ + aml_append(if_caps_masked, aml_or(a_cdw1, aml_int(0x10), a_cdw1)); + aml_append(if_cxl, if_caps_masked); + + aml_append(if_cxl, aml_store(cxl_ctrl, aml_name("CDW5"))); + aml_append(if_cxl, aml_store(aml_name("CDW4"), aml_name("SUPC"))); aml_append(if_cxl, aml_store(aml_name("CDW5"), aml_name("CTRC"))); @@ -316,11 +339,11 @@ static Aml *__build_cxl_osc_method(void) return method; } -void build_cxl_osc_method(Aml *dev) +void build_cxl_osc_method(Aml *dev, bool fw_first) { aml_append(dev, aml_name_decl("SUPP", aml_int(0))); aml_append(dev, aml_name_decl("CTRL", aml_int(0))); aml_append(dev, aml_name_decl("SUPC", aml_int(0))); aml_append(dev, aml_name_decl("CTRC", aml_int(0))); - aml_append(dev, __build_cxl_osc_method()); + aml_append(dev, __build_cxl_osc_method(fw_first)); } diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 58e4c54f31..2fbac1d826 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1655,7 +1655,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(aml_pkg, aml_eisaid("PNP0A08")); aml_append(aml_pkg, aml_eisaid("PNP0A03")); aml_append(dev, aml_name_decl("_CID", aml_pkg)); - build_cxl_osc_method(dev); + build_cxl_osc_method(dev, false); } else if (pci_bus_is_express(bus)) { aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index f69413ea2c..f003669975 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -49,7 +49,7 @@ static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq) } } -static void acpi_dsdt_add_pci_osc(Aml *dev) +static void acpi_dsdt_add_pci_osc(Aml *dev, bool fw_first_aer) { Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf; @@ -79,8 +79,13 @@ static void acpi_dsdt_add_pci_osc(Aml *dev) * Allow OS control for all 5 features: * PCIeHotplug SHPCHotplug PME AER PCIeCapability. */ - aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), - aml_name("CTRL"))); + if (fw_first_aer) { + aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x17), + aml_name("CTRL"))); + } else { + aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), + aml_name("CTRL"))); + } ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), @@ -186,9 +191,9 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) aml_append(dev, aml_name_decl("_CRS", crs)); if (is_cxl) { - build_cxl_osc_method(dev); + build_cxl_osc_method(dev, cfg->fw_first_ras); } else { - acpi_dsdt_add_pci_osc(dev); + acpi_dsdt_add_pci_osc(dev, cfg->fw_first_ras); } aml_append(scope, dev); @@ -263,7 +268,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) } aml_append(dev, aml_name_decl("_CRS", rbuf)); - acpi_dsdt_add_pci_osc(dev); + acpi_dsdt_add_pci_osc(dev, cfg->fw_first_ras); Aml *dev_res0 = aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index e9cf455bf5..49fc69eec6 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -166,6 +166,7 @@ static Property gpex_host_properties[] = { gpex_cfg.mmio64.base, 0), DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost, gpex_cfg.mmio64.size, 0), + DEFINE_PROP_BOOL("fw_first_ras", GPEXHost, gpex_cfg.fw_first_ras, false), DEFINE_PROP_END_OF_LIST(), };

[RFC,02/11] hw/acpi: Allow GPEX _OSC to keep fw first control of AER and CXL errors.

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