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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN1PEPF0000468A.mail.protection.outlook.com (10.167.243.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7292.25 via Frontend Transport; Thu, 15 Feb 2024 19:41:57 +0000 Received: from bcheatha-HP-EliteBook-845-G8-Notebook-PC.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Thu, 15 Feb 2024 13:41:55 -0600 From: Ben Cheatham To: , CC: , , , , , , , , Subject: [RFC PATCH 4/6] pcie/cxl_timeout: Add CXL.mem error isolation support Date: Thu, 15 Feb 2024 13:40:46 -0600 Message-ID: <20240215194048.141411-5-Benjamin.Cheatham@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> References: <20240215194048.141411-1-Benjamin.Cheatham@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468A:EE_|LV8PR12MB9207:EE_ X-MS-Office365-Filtering-Correlation-Id: c6779b49-ccdb-415f-ddf7-08dc2e5e2beb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2024 19:41:57.7980 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6779b49-ccdb-415f-ddf7-08dc2e5e2beb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9207 Add and enable CXL.mem error isolation support (CXL 3.0 12.3.2) to the CXL Timeout & Isolation service driver. Signed-off-by: Ben Cheatham --- drivers/cxl/cxl.h | 2 ++ drivers/pci/pcie/cxl_timeout.c | 40 +++++++++++++++++++++++++++++++++- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 4aa5fecc43bd..b1d5232a0127 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -131,9 +131,11 @@ static inline int ways_to_eiw(unsigned int ways, u8 *eiw) #define CXL_TIMEOUT_CAPABILITY_OFFSET 0x0 #define CXL_TIMEOUT_CAP_MEM_TIMEOUT_MASK GENMASK(3, 0) #define CXL_TIMEOUT_CAP_MEM_TIMEOUT_SUPP BIT(4) +#define CXL_TIMEOUT_CAP_MEM_ISO_SUPP BIT(16) #define CXL_TIMEOUT_CONTROL_OFFSET 0x8 #define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_MASK GENMASK(3, 0) #define CXL_TIMEOUT_CONTROL_MEM_TIMEOUT_ENABLE BIT(4) +#define CXL_TIMEOUT_CONTROL_MEM_ISO_ENABLE BIT(16) #define CXL_TIMEOUT_CAPABILITY_LENGTH 0x10 /* CXL 3.0 8.2.4.23.2 CXL Timeout and Isolation Control Register, bits 3:0 */ diff --git a/drivers/pci/pcie/cxl_timeout.c b/drivers/pci/pcie/cxl_timeout.c index 916dbaf2bb58..5900239e5bbf 100644 --- a/drivers/pci/pcie/cxl_timeout.c +++ b/drivers/pci/pcie/cxl_timeout.c @@ -207,6 +207,31 @@ static int cxl_enable_timeout(struct pcie_device *dev, struct cxl_timeout *cxlt) cxlt); } +static void cxl_disable_isolation(void *data) +{ + struct cxl_timeout *cxlt = data; + u32 cntrl = readl(cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + + cntrl &= ~CXL_TIMEOUT_CONTROL_MEM_ISO_ENABLE; + writel(cntrl, cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); +} + +static int cxl_enable_isolation(struct pcie_device *dev, + struct cxl_timeout *cxlt) +{ + u32 cntrl; + + if (!cxlt || !FIELD_GET(CXL_TIMEOUT_CAP_MEM_ISO_SUPP, cxlt->cap)) + return -ENXIO; + + cntrl = readl(cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + cntrl |= CXL_TIMEOUT_CONTROL_MEM_ISO_ENABLE; + writel(cntrl, cxlt->regs + CXL_TIMEOUT_CONTROL_OFFSET); + + return devm_add_action_or_reset(&dev->device, cxl_disable_isolation, + cxlt); +} + static ssize_t timeout_range_show(struct device *dev, struct device_attribute *attr, char *buf) @@ -341,7 +366,8 @@ static int cxl_timeout_probe(struct pcie_device *dev) struct pci_dev *port = dev->port; struct pcie_cxlt_data *pdata; struct cxl_timeout *cxlt; - int rc = 0; + bool timeout_enabled; + int rc; /* Limit to CXL root ports */ if (!pci_find_dvsec_capability(port, PCI_DVSEC_VENDOR_ID_CXL, @@ -360,6 +386,18 @@ static int cxl_timeout_probe(struct pcie_device *dev) pci_dbg(dev->port, "Failed to enable CXL.mem timeout: %d\n", rc); + timeout_enabled = !rc; + + rc = cxl_enable_isolation(dev, cxlt); + if (rc) + pci_dbg(dev->port, "Failed to enable CXL.mem isolation: %d\n", + rc); + + if (rc && !timeout_enabled) { + pci_info(dev->port, + "Failed to enable CXL.mem timeout and isolation.\n"); + } + return rc; }