| Message ID | 20240813110532.870869-4-yanfei.xu@intel.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Fixes for hdm docoder initialization from DVSEC ranges | expand |
On Tue, 13 Aug 2024 19:05:31 +0800 Yanfei Xu <yanfei.xu@intel.com> wrote: > The right way is to checking Mem_info_valid bit for each applicable > DVSEC range against HDM_COUNT, not only for the DVSEC range 1, hence > let's move the check into the "for loop" of handling each DVSEC range. Say why it's the 'right' way. I agree it probably is, but more detail in this patch description would be good. I assume it's as simple as "In theory a device might set the mem_info_valid bit for a first range after it is ready but before as second range has reached that state." If so looks fine to me and with that additional detail, Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > > Signed-off-by: Yanfei Xu <yanfei.xu@intel.com> > --- > drivers/cxl/core/pci.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 38c567727dbb..519989ada48e 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -324,10 +324,6 @@ int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, > if (!hdm_count || hdm_count > 2) > return -EINVAL; > > - rc = cxl_dvsec_mem_range_valid(cxlds, 0); > - if (rc) > - return rc; > - > /* > * The current DVSEC values are moot if the memory capability is > * disabled, and they will remain moot after the HDM Decoder > @@ -345,6 +341,10 @@ int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, > u64 base, size; > u32 temp; > > + rc = cxl_dvsec_mem_range_valid(cxlds, i); > + if (rc) > + return rc; > + > rc = pci_read_config_dword( > pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp); > if (rc)
On 8/28/2024 12:22 AM, Jonathan Cameron wrote: > On Tue, 13 Aug 2024 19:05:31 +0800 > Yanfei Xu <yanfei.xu@intel.com> wrote: > >> The right way is to checking Mem_info_valid bit for each applicable >> DVSEC range against HDM_COUNT, not only for the DVSEC range 1, hence >> let's move the check into the "for loop" of handling each DVSEC range. > Say why it's the 'right' way. I agree it probably is, but more > detail in this patch description would be good. > I assume it's as simple as > "In theory a device might set the mem_info_valid bit for a first range > after it is ready but before as second range has reached that state." > > If so looks fine to me and with that additional detail, > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Make sense, will do in v4. Thanks for your review! > > >> >> Signed-off-by: Yanfei Xu <yanfei.xu@intel.com> >> --- >> drivers/cxl/core/pci.c | 8 ++++---- >> 1 file changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c >> index 38c567727dbb..519989ada48e 100644 >> --- a/drivers/cxl/core/pci.c >> +++ b/drivers/cxl/core/pci.c >> @@ -324,10 +324,6 @@ int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, >> if (!hdm_count || hdm_count > 2) >> return -EINVAL; >> >> - rc = cxl_dvsec_mem_range_valid(cxlds, 0); >> - if (rc) >> - return rc; >> - >> /* >> * The current DVSEC values are moot if the memory capability is >> * disabled, and they will remain moot after the HDM Decoder >> @@ -345,6 +341,10 @@ int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, >> u64 base, size; >> u32 temp; >> >> + rc = cxl_dvsec_mem_range_valid(cxlds, i); >> + if (rc) >> + return rc; >> + >> rc = pci_read_config_dword( >> pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp); >> if (rc) > >
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 38c567727dbb..519989ada48e 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -324,10 +324,6 @@ int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, if (!hdm_count || hdm_count > 2) return -EINVAL; - rc = cxl_dvsec_mem_range_valid(cxlds, 0); - if (rc) - return rc; - /* * The current DVSEC values are moot if the memory capability is * disabled, and they will remain moot after the HDM Decoder @@ -345,6 +341,10 @@ int cxl_dvsec_rr_decode(struct device *dev, struct cxl_port *port, u64 base, size; u32 temp; + rc = cxl_dvsec_mem_range_valid(cxlds, i); + if (rc) + return rc; + rc = pci_read_config_dword( pdev, d + CXL_DVSEC_RANGE_SIZE_HIGH(i), &temp); if (rc)
The right way is to checking Mem_info_valid bit for each applicable DVSEC range against HDM_COUNT, not only for the DVSEC range 1, hence let's move the check into the "for loop" of handling each DVSEC range. Signed-off-by: Yanfei Xu <yanfei.xu@intel.com> --- drivers/cxl/core/pci.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)