[2/3] cxl/pci: cxl_dport_map_rch_aer() cleanup

Commit Message

Li, Ming4 Aug. 27, 2024, 4:57 a.m. UTC

cxl_dport_map_ras() is used to map CXL RAS capability, the RCH AER
capability should not be mapped in the function but should mapped in
cxl_dport_init_aer(). Moving cxl_dport_map_ras() out of
cxl_dport_map_ras() and into cxl_dport_init_aer().

In cxl_dport_init_aer(), the AER capability position in RCRB will be
located but the position is only used in cxl_dport_map_rch_aer(),
getting the position in cxl_dport_map_rch_aer() rather than
cxl_dport_init_aer() is more reasonable and makes the code clearer.

Besides, some local variables in cxl_dport_map_rch_aer() are
unnecessary, remove them to make the function more concise.

Signed-off-by: Li Ming <[e-mail]>
---
 drivers/cxl/core/pci.c | 33 +++++++++++++--------------------
 1 file changed, 13 insertions(+), 20 deletions(-)

Comments

Jonathan Cameron Aug. 27, 2024, 3 p.m. UTC | #1

On Tue, 27 Aug 2024 04:57:54 +0000
Li Ming <[e-mail]> wrote:

> cxl_dport_map_ras() is used to map CXL RAS capability, the RCH AER
> capability should not be mapped in the function but should mapped in
> cxl_dport_init_aer(). Moving cxl_dport_map_ras() out of
> cxl_dport_map_ras() and into cxl_dport_init_aer().
> 
> In cxl_dport_init_aer(), the AER capability position in RCRB will be
> located but the position is only used in cxl_dport_map_rch_aer(),
> getting the position in cxl_dport_map_rch_aer() rather than
> cxl_dport_init_aer() is more reasonable and makes the code clearer.
> 
> Besides, some local variables in cxl_dport_map_rch_aer() are
> unnecessary, remove them to make the function more concise.
> 
> Signed-off-by: Li Ming <[e-mail]>
Seems sensible
Reviewed-by: Jonathan Cameron <[e-mail]>

Patch

diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
index 9761178372b6..118db6a577d7 100644
--- a/drivers/cxl/core/pci.c
+++ b/drivers/cxl/core/pci.c
@@ -772,19 +772,17 @@  static bool cxl_handle_endpoint_ras(struct cxl_dev_state *cxlds)
 
 static void cxl_dport_map_rch_aer(struct cxl_dport *dport)
 {
-	struct cxl_rcrb_info *ri = &dport->rcrb;
-	void __iomem *dport_aer = NULL;
 	resource_size_t aer_phys;
 	struct device *host;
+	u16 aer_cap;
 
-	if (dport->rch && ri->aer_cap) {
+	aer_cap = cxl_rcrb_to_aer(dport->dport_dev, dport->rcrb.base);
+	if (aer_cap) {
 		host = dport->reg_map.host;
-		aer_phys = ri->aer_cap + ri->base;
-		dport_aer = devm_cxl_iomap_block(host, aer_phys,
-				sizeof(struct aer_capability_regs));
+		aer_phys = aer_cap + dport->rcrb.base;
+		dport->regs.dport_aer = devm_cxl_iomap_block(host, aer_phys,
+						sizeof(struct aer_capability_regs));
 	}
-
-	dport->regs.dport_aer = dport_aer;
 }
 
 static void cxl_dport_map_ras(struct cxl_dport *dport)
@@ -797,9 +795,6 @@  static void cxl_dport_map_ras(struct cxl_dport *dport)
 	else if (cxl_map_component_regs(map, &dport->regs.component,
 					BIT(CXL_CM_CAP_CAP_ID_RAS)))
 		dev_dbg(dev, "Failed to map RAS capability.\n");
-
-	if (dport->rch)
-		cxl_dport_map_rch_aer(dport);
 }
 
 static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
@@ -838,20 +833,18 @@  static void cxl_disable_rch_root_ints(struct cxl_dport *dport)
  */
 void cxl_dport_init_aer(struct cxl_dport *dport, struct device *host)
 {
-	struct device *dport_dev = dport->dport_dev;
+	dport->reg_map.host = host;
+	cxl_dport_map_ras(dport);
 
 	if (dport->rch) {
-		struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport_dev);
-
-		if (host_bridge->native_aer)
-			dport->rcrb.aer_cap = cxl_rcrb_to_aer(dport_dev, dport->rcrb.base);
-	}
+		struct pci_host_bridge *host_bridge = to_pci_host_bridge(dport->dport_dev);
 
-	dport->reg_map.host = host;
-	cxl_dport_map_ras(dport);
+		if (!host_bridge->native_aer)
+			return;
 
-	if (dport->rch)
+		cxl_dport_map_rch_aer(dport);
 		cxl_disable_rch_root_ints(dport);
+	}
 }
 EXPORT_SYMBOL_NS_GPL(cxl_dport_init_aer, CXL);