| Message ID | 20240827045755.1837473-3-ming4.li@intel.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [1/3] cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs() | expand |
On Tue, 27 Aug 2024 04:57:55 +0000 Li Ming <ming4.li@intel.com> wrote: > cxl_dport_init_aer() already checks host_bridge->native_aer before > invoking cxl_disable_rch_root_ints(), so cxl_disable_rch_root_ints() > does not need to check it again. > > Signed-off-by: Li Ming <ming4.li@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
On Tue, 27 Aug 2024 04:57:55 +0000 Li Ming <ming4.li@intel.com> wrote: For title, just duplicate (not reduplicate) > cxl_dport_init_aer() already checks host_bridge->native_aer before > invoking cxl_disable_rch_root_ints(), so cxl_disable_rch_root_ints() > does not need to check it again. > > Signed-off-by: Li Ming <ming4.li@intel.com> > --- > drivers/cxl/core/pci.c | 17 ++++++----------- > 1 file changed, 6 insertions(+), 11 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 118db6a577d7..7234166df0df 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -800,14 +800,11 @@ static void cxl_dport_map_ras(struct cxl_dport *dport) > static void cxl_disable_rch_root_ints(struct cxl_dport *dport) > { > void __iomem *aer_base = dport->regs.dport_aer; > - struct pci_host_bridge *bridge; > u32 aer_cmd_mask, aer_cmd; > > if (!aer_base) > return; > > - bridge = to_pci_host_bridge(dport->dport_dev); > - > /* > * Disable RCH root port command interrupts. > * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors > @@ -816,14 +813,12 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport) > * the root cmd register's interrupts is required. But, PCI spec > * shows these are disabled by default on reset. > */ > - if (bridge->native_aer) { > - aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN | > - PCI_ERR_ROOT_CMD_NONFATAL_EN | > - PCI_ERR_ROOT_CMD_FATAL_EN); > - aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND); > - aer_cmd &= ~aer_cmd_mask; > - writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); > - } > + aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN | > + PCI_ERR_ROOT_CMD_NONFATAL_EN | > + PCI_ERR_ROOT_CMD_FATAL_EN); > + aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND); > + aer_cmd &= ~aer_cmd_mask; > + writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); > } > > /**
On 8/28/2024 4:21 PM, Jonathan Cameron wrote: > On Tue, 27 Aug 2024 04:57:55 +0000 > Li Ming <ming4.li@intel.com> wrote: > > For title, just duplicate (not reduplicate) Got it, thanks. > >> cxl_dport_init_aer() already checks host_bridge->native_aer before >> invoking cxl_disable_rch_root_ints(), so cxl_disable_rch_root_ints() >> does not need to check it again. >> >> Signed-off-by: Li Ming <ming4.li@intel.com> >> --- >> drivers/cxl/core/pci.c | 17 ++++++----------- >> 1 file changed, 6 insertions(+), 11 deletions(-) >> >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c >> index 118db6a577d7..7234166df0df 100644 >> --- a/drivers/cxl/core/pci.c >> +++ b/drivers/cxl/core/pci.c >> @@ -800,14 +800,11 @@ static void cxl_dport_map_ras(struct cxl_dport *dport) >> static void cxl_disable_rch_root_ints(struct cxl_dport *dport) >> { >> void __iomem *aer_base = dport->regs.dport_aer; >> - struct pci_host_bridge *bridge; >> u32 aer_cmd_mask, aer_cmd; >> >> if (!aer_base) >> return; >> >> - bridge = to_pci_host_bridge(dport->dport_dev); >> - >> /* >> * Disable RCH root port command interrupts. >> * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors >> @@ -816,14 +813,12 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport) >> * the root cmd register's interrupts is required. But, PCI spec >> * shows these are disabled by default on reset. >> */ >> - if (bridge->native_aer) { >> - aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN | >> - PCI_ERR_ROOT_CMD_NONFATAL_EN | >> - PCI_ERR_ROOT_CMD_FATAL_EN); >> - aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND); >> - aer_cmd &= ~aer_cmd_mask; >> - writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); >> - } >> + aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN | >> + PCI_ERR_ROOT_CMD_NONFATAL_EN | >> + PCI_ERR_ROOT_CMD_FATAL_EN); >> + aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND); >> + aer_cmd &= ~aer_cmd_mask; >> + writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); >> } >> >> /** >
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 118db6a577d7..7234166df0df 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -800,14 +800,11 @@ static void cxl_dport_map_ras(struct cxl_dport *dport) static void cxl_disable_rch_root_ints(struct cxl_dport *dport) { void __iomem *aer_base = dport->regs.dport_aer; - struct pci_host_bridge *bridge; u32 aer_cmd_mask, aer_cmd; if (!aer_base) return; - bridge = to_pci_host_bridge(dport->dport_dev); - /* * Disable RCH root port command interrupts. * CXL 3.0 12.2.1.1 - RCH Downstream Port-detected Errors @@ -816,14 +813,12 @@ static void cxl_disable_rch_root_ints(struct cxl_dport *dport) * the root cmd register's interrupts is required. But, PCI spec * shows these are disabled by default on reset. */ - if (bridge->native_aer) { - aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN | - PCI_ERR_ROOT_CMD_NONFATAL_EN | - PCI_ERR_ROOT_CMD_FATAL_EN); - aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND); - aer_cmd &= ~aer_cmd_mask; - writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); - } + aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN | + PCI_ERR_ROOT_CMD_NONFATAL_EN | + PCI_ERR_ROOT_CMD_FATAL_EN); + aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND); + aer_cmd &= ~aer_cmd_mask; + writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); } /**
cxl_dport_init_aer() already checks host_bridge->native_aer before invoking cxl_disable_rch_root_ints(), so cxl_disable_rch_root_ints() does not need to check it again. Signed-off-by: Li Ming <ming4.li@intel.com> --- drivers/cxl/core/pci.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-)