| Message ID | 20240828084231.1378789-2-yanfei.xu@intel.com |
|---|---|
| State | Accepted |
| Commit | 55e268694e8b07026c88191f9b6949b6887d9ce3 |
| Headers | show |
| Series | cxl: Fixes for hdm decoder initialization from DVSEC ranges | expand |
On Wed, Aug 28, 2024 at 04:42:28PM +0800, Yanfei Xu wrote: > The function cxl_dvsec_rr_decode() retrieves and records DVSEC ranges > into info->dvsec_range[], regardless of whether it is non-zero range, > and the variable info->ranges indicates the number of non-zero ranges. > However, in cxl_hdm_decode_init(), the validation for > info->dvsec_range[] occurs in a for loop that iterates based on > info->ranges. It may result in zero range to be validated but non-zero > range not be validated, in turn, the number of allowed ranges is to be > 0. Address it by only record non-zero ranges. > > This fix is not urgent as it requires a configuration that zeroes out > the first dvsec range while populating the second. This has not been > observed, but it is theoretically possible. If this gets picked up for > -stable, no harm done, but there is no urgency to backport. > I'd prefer the commit msg be: cxl/pci: Record only non-zero DVSEC ranges but either way - Reviewed-by: Alison Schofield <alison.schofield@intel.com> > Fixes: 560f78559006 ("cxl/pci: Retrieve CXL DVSEC memory info") > Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > Signed-off-by: Yanfei Xu <yanfei.xu@intel.com> > --- > drivers/cxl/core/pci.c | 8 +------- > 1 file changed, 1 insertion(+), 7 deletions(-) snip
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 51132a575b27..73b6498d5e5c 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -390,10 +390,6 @@ int cxl_dvsec_rr_decode(struct device *dev, int d, size |= temp & CXL_DVSEC_MEM_SIZE_LOW_MASK; if (!size) { - info->dvsec_range[i] = (struct range) { - .start = 0, - .end = CXL_RESOURCE_NONE, - }; continue; } @@ -411,12 +407,10 @@ int cxl_dvsec_rr_decode(struct device *dev, int d, base |= temp & CXL_DVSEC_MEM_BASE_LOW_MASK; - info->dvsec_range[i] = (struct range) { + info->dvsec_range[ranges++] = (struct range) { .start = base, .end = base + size - 1 }; - - ranges++; } info->ranges = ranges;
The function cxl_dvsec_rr_decode() retrieves and records DVSEC ranges into info->dvsec_range[], regardless of whether it is non-zero range, and the variable info->ranges indicates the number of non-zero ranges. However, in cxl_hdm_decode_init(), the validation for info->dvsec_range[] occurs in a for loop that iterates based on info->ranges. It may result in zero range to be validated but non-zero range not be validated, in turn, the number of allowed ranges is to be 0. Address it by only record non-zero ranges. This fix is not urgent as it requires a configuration that zeroes out the first dvsec range while populating the second. This has not been observed, but it is theoretically possible. If this gets picked up for -stable, no harm done, but there is no urgency to backport. Fixes: 560f78559006 ("cxl/pci: Retrieve CXL DVSEC memory info") Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Yanfei Xu <yanfei.xu@intel.com> --- drivers/cxl/core/pci.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-)