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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C Received: from SATLEXMB03.amd.com (165.204.84.17) by DS1PEPF0001709D.mail.protection.outlook.com (10.167.18.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7918.13 via Frontend Transport; Sat, 7 Sep 2024 08:19:24 +0000 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Sat, 7 Sep 2024 03:19:23 -0500 Received: from xcbalucerop41x.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39 via Frontend Transport; Sat, 7 Sep 2024 03:19:22 -0500 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v3 03/20] cxl/pci: add check for validating capabilities Date: Sat, 7 Sep 2024 09:18:19 +0100 Message-ID: <20240907081836.5801-4-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240907081836.5801-1-alejandro.lucero-palau@amd.com> References: <20240907081836.5801-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Received-SPF: None (SATLEXMB03.amd.com: alejandro.lucero-palau@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0001709D:EE_|MW6PR12MB8959:EE_ X-MS-Office365-Filtering-Correlation-Id: e450b5d3-8568-40b5-f999-08dccf15c858 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014; X-Microsoft-Antispam-Message-Info: g9dpocshBMwM3YKrfYPR1PzgldIgljFlBPAT3CZjG60hZ4girt/RzLSpGiiwuUUH4OdFndggb1lWEP0v+yN/A6CWVufsqy+yEm1H/toBuWIfd9e1DgkbBqA1NB0UaCu5N7Yq7YcTl+4Ut1vBS5fl2BN09l91vl0Yga4X76ZTuFR8zhuY8Pg85ro6KaNf0gG6nr8lPby3urPkGPOew1pl9zPuqLknV0YMGgbVSI4vNCPuQM5yVYk8pHX6t41oeGHymaRunGQH1rm1KOOQ2HYSPiGOyFwyf2mjYOLmrmeqCdK6pTBo79SRAhbToXu0GcmJ76in4y5sBEtkY59+9sEJ4Lm2diz/qzT0AMxTEiFz3WIdY94fj9i650aftBHSDENr8xyguQGQvMD4/GGuZc12VlElEZ2elQ00ff3hG43ciG4UKkgsBDoUfZnFmC4ZDx/qz2cpq+i06+XxkNjvKE4kXSvnQFGBNJ8oGEipOaBD4iD9hBaAsnCEzxvvj3u8tH0f7Se0gTcYh0iQZ7zkIt3kBYeYamK4iFAeuYXyIuljrg2u0PRNc98DfIuEFdW99lGoAm/8PHbWlkfplfdielmas/kmkw5p3WK+DyvTINDZfNEHmk2bYAlhIWur3ZQzotsZb2Zle01capGUw837IJ96CtGDewabA1nv7Ahf4XOe6aAtEGn3kj7EdmetJCfuaL+NIH/x8kPPf5y33sj3acOt0+SnQfOVkTAPcTSYQWIb/B+X5DdLmMfxuoxL+LzV3T6dgarWmOwyzCANbGewtpDCDtgku5JPRfdGTYkE8aseFu9pC22lYUvUojAquQC2rsyqWN50Lj+9fEIMwgv5rFCkbmjfSevqDYY1icSqpVXbc41Il2G2NFjCiWBERYklD9VGKH5gpa/Abn2XGFoPTVB/9WHR1pQeNapcVNuWz0QryBmVl2tokGlCfSW5YsvlkqpSjGLPnefYo4zOWt88uI0uIKTU79KJKsmadvn2MNZzFGa5eKsITF3z7uBFsAXdn97soNDeFOeeZQDQdqyRlatxJrhU6cbdeh7HMofaxmM5pmmToqGNR+5tWPwgm4f9Eo5fwJIVcoxEkFiLuyTB3yJpDhKKiC53NntnKSJ3yD1i7ulfJYOZIwoN6jCuwOPbA8tWTuCmmXs4tl7HKD+aLthxrCI9qbWScoZpb/TEDoeOgaRQ6/XR/E4z2zSny8/HP1PrXaEbFWMat9TgUy7sU9E2IIaAmVZxnCxZaadUTDFnbP698FOenU6IvE9uTaCyvfBuY5U8N8cOfA3z5LfuDUyyXFKWiMkcIREhmsUawNazTuOC//3ZVrmztmCxut/aSOk7+IvxKYbG2CYGokgzL1ltIHZdy84DC332UzZ/LQCGYfeKg0F3/xVLSA0yJrHfjy6DpoSS/bZXUpbidCVPhQYu9AZjl227yD3cBbZSw3Hb4yICB1uik5bwl3/s+Io4J9bb X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Sep 2024 08:19:24.1211 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e450b5d3-8568-40b5-f999-08dccf15c858 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0001709D.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8959 From: Alejandro Lucero During CXL device initialization supported capabilities by the device are discovered. Type3 and Type2 devices have different mandatory capabilities and a Type2 expects a specific set including optional capabilities. Add a function for checking expected capabilities against those found during initialization. Rely on this function for validating capabilities instead of when CXL regs are probed. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/pci.c | 17 +++++++++++++++++ drivers/cxl/core/regs.c | 9 --------- drivers/cxl/pci.c | 12 ++++++++++++ include/linux/cxl/cxl.h | 2 ++ 4 files changed, 31 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 3d6564dbda57..57370d9beb32 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1077,3 +1078,19 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) __cxl_endpoint_decoder_reset_detected); } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, CXL); + +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, u32 expected_caps, + u32 *current_caps) +{ + if (current_caps) + *current_caps = cxlds->capabilities; + + dev_dbg(cxlds->dev, "Checking cxlds caps 0x%08x vs expected caps 0x%08x\n", + cxlds->capabilities, expected_caps); + + if ((cxlds->capabilities & expected_caps) != expected_caps) + return false; + + return true; +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_check_caps, CXL); diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 8b8abcadcb93..35f6dc97be6e 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -443,15 +443,6 @@ static int cxl_probe_regs(struct cxl_register_map *map, u32 *caps) case CXL_REGLOC_RBI_MEMDEV: dev_map = &map->device_map; cxl_probe_device_regs(host, base, dev_map, caps); - if (!dev_map->status.valid || !dev_map->mbox.valid || - !dev_map->memdev.valid) { - dev_err(host, "registers not found: %s%s%s\n", - !dev_map->status.valid ? "status " : "", - !dev_map->mbox.valid ? "mbox " : "", - !dev_map->memdev.valid ? "memdev " : ""); - return -ENXIO; - } - dev_dbg(host, "Probing device registers...\n"); break; default: diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 58f325019886..bec660357eec 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -796,6 +796,7 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) struct cxl_register_map map; struct cxl_memdev *cxlmd; int i, rc, pmu_count; + u32 expected, found; bool irq_avail; u16 dvsec; @@ -852,6 +853,17 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + /* These are the mandatory capabilities for a Type3 device */ + expected = BIT(CXL_DEV_CAP_HDM) | BIT(CXL_DEV_CAP_DEV_STATUS) | + BIT(CXL_DEV_CAP_MAILBOX_PRIMARY) | BIT(CXL_DEV_CAP_MEMDEV); + + if (!cxl_pci_check_caps(cxlds, expected, &found)) { + dev_err(&pdev->dev, + "Expected capabilities not matching with found capabilities: (%08x - %08x)\n", + expected, found); + return -ENXIO; + } + rc = cxl_await_media_ready(cxlds); if (rc == 0) cxlds->media_ready = true; diff --git a/include/linux/cxl/cxl.h b/include/linux/cxl/cxl.h index 930b1b9c1d6a..4a57bf60403d 100644 --- a/include/linux/cxl/cxl.h +++ b/include/linux/cxl/cxl.h @@ -48,4 +48,6 @@ void cxl_set_dvsec(struct cxl_dev_state *cxlds, u16 dvsec); void cxl_set_serial(struct cxl_dev_state *cxlds, u64 serial); int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, enum cxl_resource); +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, u32 expected_caps, + u32 *current_caps); #endif