| Message ID | 20240907081836.5801-5-alejandro.lucero-palau@amd.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | cxl: add Type2 device support | expand |
On 9/7/24 1:18 AM, alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero <alucerop@amd.com> > > Inside cxl/core/pci.c there are helpers for CXL PCIe initialization > meanwhile cxl/pci.c implements the functionality for a Type3 device > initialization. > > Move those functions required also for Type2 initialization to > cxl/core/pci.c with a specific function using that moved code added in > a following patch. Please consider rephrasing as: Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be exported and shared with CXL Type2 device initialization. > > Signed-off-by: Alejandro Lucero <alucerop@amd.com> > --- > drivers/cxl/core/pci.c | 63 ++++++++++++++++++++++++++++++++++++++++++ > drivers/cxl/cxlpci.h | 3 ++ > drivers/cxl/pci.c | 60 ---------------------------------------- > 3 files changed, 66 insertions(+), 60 deletions(-) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index 57370d9beb32..bf57f081ef8f 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -1079,6 +1079,69 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) > } > EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, CXL); > > +/* > + * Assume that any RCIEP that emits the CXL memory expander class code > + * is an RCD > + */ > +bool is_cxl_restricted(struct pci_dev *pdev) > +{ > + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; > +} > +EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, CXL); > + > +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, > + struct cxl_register_map *map) > +{ > + struct cxl_port *port; > + struct cxl_dport *dport; > + resource_size_t component_reg_phys; > + > + *map = (struct cxl_register_map) { > + .host = &pdev->dev, > + .resource = CXL_RESOURCE_NONE, > + }; > + > + port = cxl_pci_find_port(pdev, &dport); > + if (!port) > + return -EPROBE_DEFER; > + > + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); > + > + put_device(&port->dev); > + > + if (component_reg_phys == CXL_RESOURCE_NONE) > + return -ENXIO; > + > + map->resource = component_reg_phys; > + map->reg_type = CXL_REGLOC_RBI_COMPONENT; > + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; > + > + return 0; > +} > + > +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > + struct cxl_register_map *map, > + u32 *caps) > +{ > + int rc; > + > + rc = cxl_find_regblock(pdev, type, map); > + > + /* > + * If the Register Locator DVSEC does not exist, check if it > + * is an RCH and try to extract the Component Registers from > + * an RCRB. > + */ > + if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) > + rc = cxl_rcrb_get_comp_regs(pdev, map); > + > + if (rc) > + return rc; > + > + return cxl_setup_regs(map, caps); > +} > +EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); > + > bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, u32 expected_caps, > u32 *current_caps) > { > diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h > index eb59019fe5f3..786b811effba 100644 > --- a/drivers/cxl/cxlpci.h > +++ b/drivers/cxl/cxlpci.h > @@ -113,4 +113,7 @@ void read_cdat_data(struct cxl_port *port); > void cxl_cor_error_detected(struct pci_dev *pdev); > pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, > pci_channel_state_t state); > +bool is_cxl_restricted(struct pci_dev *pdev); > +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > + struct cxl_register_map *map, u32 *caps); Does this need to go to a different header like include/cxl/pci.h or something for type2 consumption? DJ > #endif /* __CXL_PCI_H__ */ > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index bec660357eec..2b85f87549c2 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -463,66 +463,6 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail) > return 0; > } > > -/* > - * Assume that any RCIEP that emits the CXL memory expander class code > - * is an RCD > - */ > -static bool is_cxl_restricted(struct pci_dev *pdev) > -{ > - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; > -} > - > -static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, > - struct cxl_register_map *map) > -{ > - struct cxl_port *port; > - struct cxl_dport *dport; > - resource_size_t component_reg_phys; > - > - *map = (struct cxl_register_map) { > - .host = &pdev->dev, > - .resource = CXL_RESOURCE_NONE, > - }; > - > - port = cxl_pci_find_port(pdev, &dport); > - if (!port) > - return -EPROBE_DEFER; > - > - component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); > - > - put_device(&port->dev); > - > - if (component_reg_phys == CXL_RESOURCE_NONE) > - return -ENXIO; > - > - map->resource = component_reg_phys; > - map->reg_type = CXL_REGLOC_RBI_COMPONENT; > - map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; > - > - return 0; > -} > - > -static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > - struct cxl_register_map *map, u32 *caps) > -{ > - int rc; > - > - rc = cxl_find_regblock(pdev, type, map); > - > - /* > - * If the Register Locator DVSEC does not exist, check if it > - * is an RCH and try to extract the Component Registers from > - * an RCRB. > - */ > - if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) > - rc = cxl_rcrb_get_comp_regs(pdev, map); > - > - if (rc) > - return rc; > - > - return cxl_setup_regs(map, caps); > -} > - > static int cxl_pci_ras_unmask(struct pci_dev *pdev) > { > struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
On 9/12/24 00:55, Dave Jiang wrote: > > On 9/7/24 1:18 AM, alejandro.lucero-palau@amd.com wrote: >> From: Alejandro Lucero <alucerop@amd.com> >> >> Inside cxl/core/pci.c there are helpers for CXL PCIe initialization >> meanwhile cxl/pci.c implements the functionality for a Type3 device >> initialization. >> >> Move those functions required also for Type2 initialization to >> cxl/core/pci.c with a specific function using that moved code added in >> a following patch. > Please consider rephrasing as: > > Move helper functions from cxl/pci.c to cxl/core/pci.c in order to be > exported and shared with CXL Type2 device initialization. It makes sense. I'll do. >> Signed-off-by: Alejandro Lucero <alucerop@amd.com> >> --- >> drivers/cxl/core/pci.c | 63 ++++++++++++++++++++++++++++++++++++++++++ >> drivers/cxl/cxlpci.h | 3 ++ >> drivers/cxl/pci.c | 60 ---------------------------------------- >> 3 files changed, 66 insertions(+), 60 deletions(-) >> >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c >> index 57370d9beb32..bf57f081ef8f 100644 >> --- a/drivers/cxl/core/pci.c >> +++ b/drivers/cxl/core/pci.c >> @@ -1079,6 +1079,69 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) >> } >> EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, CXL); >> >> +/* >> + * Assume that any RCIEP that emits the CXL memory expander class code >> + * is an RCD >> + */ >> +bool is_cxl_restricted(struct pci_dev *pdev) >> +{ >> + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; >> +} >> +EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, CXL); >> + >> +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, >> + struct cxl_register_map *map) >> +{ >> + struct cxl_port *port; >> + struct cxl_dport *dport; >> + resource_size_t component_reg_phys; >> + >> + *map = (struct cxl_register_map) { >> + .host = &pdev->dev, >> + .resource = CXL_RESOURCE_NONE, >> + }; >> + >> + port = cxl_pci_find_port(pdev, &dport); >> + if (!port) >> + return -EPROBE_DEFER; >> + >> + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); >> + >> + put_device(&port->dev); >> + >> + if (component_reg_phys == CXL_RESOURCE_NONE) >> + return -ENXIO; >> + >> + map->resource = component_reg_phys; >> + map->reg_type = CXL_REGLOC_RBI_COMPONENT; >> + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; >> + >> + return 0; >> +} >> + >> +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, >> + struct cxl_register_map *map, >> + u32 *caps) >> +{ >> + int rc; >> + >> + rc = cxl_find_regblock(pdev, type, map); >> + >> + /* >> + * If the Register Locator DVSEC does not exist, check if it >> + * is an RCH and try to extract the Component Registers from >> + * an RCRB. >> + */ >> + if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) >> + rc = cxl_rcrb_get_comp_regs(pdev, map); >> + >> + if (rc) >> + return rc; >> + >> + return cxl_setup_regs(map, caps); >> +} >> +EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); >> + >> bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, u32 expected_caps, >> u32 *current_caps) >> { >> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h >> index eb59019fe5f3..786b811effba 100644 >> --- a/drivers/cxl/cxlpci.h >> +++ b/drivers/cxl/cxlpci.h >> @@ -113,4 +113,7 @@ void read_cdat_data(struct cxl_port *port); >> void cxl_cor_error_detected(struct pci_dev *pdev); >> pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, >> pci_channel_state_t state); >> +bool is_cxl_restricted(struct pci_dev *pdev); >> +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, >> + struct cxl_register_map *map, u32 *caps); > Does this need to go to a different header like include/cxl/pci.h or something for type2 consumption? > > DJ Next patch introduces another function for accel drivers which calls this one, hiding things for accel drivers and improving manageability. Thanks >> #endif /* __CXL_PCI_H__ */ >> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c >> index bec660357eec..2b85f87549c2 100644 >> --- a/drivers/cxl/pci.c >> +++ b/drivers/cxl/pci.c >> @@ -463,66 +463,6 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail) >> return 0; >> } >> >> -/* >> - * Assume that any RCIEP that emits the CXL memory expander class code >> - * is an RCD >> - */ >> -static bool is_cxl_restricted(struct pci_dev *pdev) >> -{ >> - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; >> -} >> - >> -static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, >> - struct cxl_register_map *map) >> -{ >> - struct cxl_port *port; >> - struct cxl_dport *dport; >> - resource_size_t component_reg_phys; >> - >> - *map = (struct cxl_register_map) { >> - .host = &pdev->dev, >> - .resource = CXL_RESOURCE_NONE, >> - }; >> - >> - port = cxl_pci_find_port(pdev, &dport); >> - if (!port) >> - return -EPROBE_DEFER; >> - >> - component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); >> - >> - put_device(&port->dev); >> - >> - if (component_reg_phys == CXL_RESOURCE_NONE) >> - return -ENXIO; >> - >> - map->resource = component_reg_phys; >> - map->reg_type = CXL_REGLOC_RBI_COMPONENT; >> - map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; >> - >> - return 0; >> -} >> - >> -static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, >> - struct cxl_register_map *map, u32 *caps) >> -{ >> - int rc; >> - >> - rc = cxl_find_regblock(pdev, type, map); >> - >> - /* >> - * If the Register Locator DVSEC does not exist, check if it >> - * is an RCH and try to extract the Component Registers from >> - * an RCRB. >> - */ >> - if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) >> - rc = cxl_rcrb_get_comp_regs(pdev, map); >> - >> - if (rc) >> - return rc; >> - >> - return cxl_setup_regs(map, caps); >> -} >> - >> static int cxl_pci_ras_unmask(struct pci_dev *pdev) >> { >> struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 57370d9beb32..bf57f081ef8f 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -1079,6 +1079,69 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, CXL); +/* + * Assume that any RCIEP that emits the CXL memory expander class code + * is an RCD + */ +bool is_cxl_restricted(struct pci_dev *pdev) +{ + return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; +} +EXPORT_SYMBOL_NS_GPL(is_cxl_restricted, CXL); + +static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, + struct cxl_register_map *map) +{ + struct cxl_port *port; + struct cxl_dport *dport; + resource_size_t component_reg_phys; + + *map = (struct cxl_register_map) { + .host = &pdev->dev, + .resource = CXL_RESOURCE_NONE, + }; + + port = cxl_pci_find_port(pdev, &dport); + if (!port) + return -EPROBE_DEFER; + + component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); + + put_device(&port->dev); + + if (component_reg_phys == CXL_RESOURCE_NONE) + return -ENXIO; + + map->resource = component_reg_phys; + map->reg_type = CXL_REGLOC_RBI_COMPONENT; + map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; + + return 0; +} + +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map, + u32 *caps) +{ + int rc; + + rc = cxl_find_regblock(pdev, type, map); + + /* + * If the Register Locator DVSEC does not exist, check if it + * is an RCH and try to extract the Component Registers from + * an RCRB. + */ + if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) + rc = cxl_rcrb_get_comp_regs(pdev, map); + + if (rc) + return rc; + + return cxl_setup_regs(map, caps); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_setup_regs, CXL); + bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, u32 expected_caps, u32 *current_caps) { diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index eb59019fe5f3..786b811effba 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -113,4 +113,7 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); +bool is_cxl_restricted(struct pci_dev *pdev); +int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, + struct cxl_register_map *map, u32 *caps); #endif /* __CXL_PCI_H__ */ diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index bec660357eec..2b85f87549c2 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -463,66 +463,6 @@ static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail) return 0; } -/* - * Assume that any RCIEP that emits the CXL memory expander class code - * is an RCD - */ -static bool is_cxl_restricted(struct pci_dev *pdev) -{ - return pci_pcie_type(pdev) == PCI_EXP_TYPE_RC_END; -} - -static int cxl_rcrb_get_comp_regs(struct pci_dev *pdev, - struct cxl_register_map *map) -{ - struct cxl_port *port; - struct cxl_dport *dport; - resource_size_t component_reg_phys; - - *map = (struct cxl_register_map) { - .host = &pdev->dev, - .resource = CXL_RESOURCE_NONE, - }; - - port = cxl_pci_find_port(pdev, &dport); - if (!port) - return -EPROBE_DEFER; - - component_reg_phys = cxl_rcd_component_reg_phys(&pdev->dev, dport); - - put_device(&port->dev); - - if (component_reg_phys == CXL_RESOURCE_NONE) - return -ENXIO; - - map->resource = component_reg_phys; - map->reg_type = CXL_REGLOC_RBI_COMPONENT; - map->max_size = CXL_COMPONENT_REG_BLOCK_SIZE; - - return 0; -} - -static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, - struct cxl_register_map *map, u32 *caps) -{ - int rc; - - rc = cxl_find_regblock(pdev, type, map); - - /* - * If the Register Locator DVSEC does not exist, check if it - * is an RCH and try to extract the Component Registers from - * an RCRB. - */ - if (rc && type == CXL_REGLOC_RBI_COMPONENT && is_cxl_restricted(pdev)) - rc = cxl_rcrb_get_comp_regs(pdev, map); - - if (rc) - return rc; - - return cxl_setup_regs(map, caps); -} - static int cxl_pci_ras_unmask(struct pci_dev *pdev) { struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);