| Message ID | 20240916173518.1843023-2-Jonathan.Cameron@huawei.com |
|---|---|
| State | New |
| Headers | show |
| Series | hw/cxl: Link speed and width control | expand |
On Mon, Sep 16, 2024 at 06:35:13PM +0100, Jonathan Cameron wrote: > Approach copied from gen_pcie_root_port.c > Previously the link defaulted to a maximum of 2.5GT/s and 1x. Enable setting > it's maximum values. The actual value after 'training' will depend on the > downstream device configuration. > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > hw/pci-bridge/cxl_root_port.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c > index 2dd10239bd..5e2156d7ba 100644 > --- a/hw/pci-bridge/cxl_root_port.c > +++ b/hw/pci-bridge/cxl_root_port.c > @@ -24,6 +24,7 @@ > #include "hw/pci/pcie_port.h" > #include "hw/pci/msi.h" > #include "hw/qdev-properties.h" > +#include "hw/qdev-properties-system.h" > #include "hw/sysbus.h" > #include "qapi/error.h" > #include "hw/cxl/cxl.h" > @@ -206,6 +207,10 @@ static Property gen_rp_props[] = { > -1), > DEFINE_PROP_SIZE("pref64-reserve", CXLRootPort, res_reserve.mem_pref_64, > -1), > + DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, > + speed, PCIE_LINK_SPEED_64), > + DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, > + width, PCIE_LINK_WIDTH_32), > DEFINE_PROP_END_OF_LIST() > }; LGTM. Reviewed-by: Fan Ni <fan.ni@samsung.com> Fan > > -- > 2.43.0 >
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 2dd10239bd..5e2156d7ba 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -24,6 +24,7 @@ #include "hw/pci/pcie_port.h" #include "hw/pci/msi.h" #include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" #include "hw/sysbus.h" #include "qapi/error.h" #include "hw/cxl/cxl.h" @@ -206,6 +207,10 @@ static Property gen_rp_props[] = { -1), DEFINE_PROP_SIZE("pref64-reserve", CXLRootPort, res_reserve.mem_pref_64, -1), + DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot, + speed, PCIE_LINK_SPEED_64), + DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, + width, PCIE_LINK_WIDTH_32), DEFINE_PROP_END_OF_LIST() };
Approach copied from gen_pcie_root_port.c Previously the link defaulted to a maximum of 2.5GT/s and 1x. Enable setting it's maximum values. The actual value after 'training' will depend on the downstream device configuration. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> --- hw/pci-bridge/cxl_root_port.c | 5 +++++ 1 file changed, 5 insertions(+)