| Message ID | 20240920223446.1908673-2-zhiw@nvidia.com |
|---|---|
| State | New |
| Headers | show |
| Series | vfio: introduce vfio-cxl to support CXL type-2 accelerator passthrough | expand |
> From: Zhi Wang <zhiw@nvidia.com> > Sent: Saturday, September 21, 2024 6:35 AM > > CXL memory device registers provide additional information about device > memory and advanced control interface for type-3 device. > > However, it is not mandatory for a type-2 device. A type-2 device can > have HDMs but not CXL memory device registers. > > Allow a type-2 device not to hanve memory device register when probing > CXL registers. this is nothing vfio specific. > > Signed-off-by: Zhi Wang <zhiw@nvidia.com> > --- > drivers/cxl/pci.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index e00ce7f4d0f9..3fbee31995f1 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -529,13 +529,13 @@ int cxl_pci_accel_setup_regs(struct pci_dev *pdev, > struct cxl_dev_state *cxlds) > int rc; > > rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > - cxlds->capabilities); > - if (rc) > - return rc; > - > - rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); > - if (rc) > - return rc; > + cxlds->capabilities); > + if (!rc) { > + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); > + if (rc) > + dev_dbg(&pdev->dev, > + "Failed to map device registers.\n"); > + } > > rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > &cxlds->reg_map, cxlds->capabilities); > -- > 2.34.1
On 9/20/24 3:34 PM, Zhi Wang wrote: > CXL memory device registers provide additional information about device > memory and advanced control interface for type-3 device. > > However, it is not mandatory for a type-2 device. A type-2 device can > have HDMs but not CXL memory device registers. > > Allow a type-2 device not to hanve memory device register when probing > CXL registers. > > Signed-off-by: Zhi Wang <zhiw@nvidia.com> > --- > drivers/cxl/pci.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index e00ce7f4d0f9..3fbee31995f1 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -529,13 +529,13 @@ int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) > int rc; > > rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, > - cxlds->capabilities); > - if (rc) > - return rc; > - > - rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); > - if (rc) > - return rc; > + cxlds->capabilities); > + if (!rc) { Given that device registers are mandatory for type3 devices, I don't think we should alter the current behavior where the code attempt to map device registers and fail if that doesn't exist. Maybe need to check against the capabilities that Alejandro introduced. DJ > + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); > + if (rc) > + dev_dbg(&pdev->dev, > + "Failed to map device registers.\n"); > + } > > rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, > &cxlds->reg_map, cxlds->capabilities);
On 23/09/2024 18.38, Dave Jiang wrote: > External email: Use caution opening links or attachments > > > On 9/20/24 3:34 PM, Zhi Wang wrote: >> CXL memory device registers provide additional information about device >> memory and advanced control interface for type-3 device. >> >> However, it is not mandatory for a type-2 device. A type-2 device can >> have HDMs but not CXL memory device registers. >> >> Allow a type-2 device not to hanve memory device register when probing >> CXL registers. >> >> Signed-off-by: Zhi Wang <zhiw@nvidia.com> >> --- >> drivers/cxl/pci.c | 14 +++++++------- >> 1 file changed, 7 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c >> index e00ce7f4d0f9..3fbee31995f1 100644 >> --- a/drivers/cxl/pci.c >> +++ b/drivers/cxl/pci.c >> @@ -529,13 +529,13 @@ int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) >> int rc; >> >> rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, >> - cxlds->capabilities); >> - if (rc) >> - return rc; >> - >> - rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); >> - if (rc) >> - return rc; >> + cxlds->capabilities); >> + if (!rc) { > > Given that device registers are mandatory for type3 devices, I don't think we should alter the current behavior where the code attempt to map device registers and fail if that doesn't exist. Maybe need to check against the capabilities that Alejandro introduced. > > DJ > Correct. This patch will be dropped when rebased to Alejandro's latest PATCHv3, which has had the checking against the capabilities. >> + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); >> + if (rc) >> + dev_dbg(&pdev->dev, >> + "Failed to map device registers.\n"); >> + } >> >> rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, >> &cxlds->reg_map, cxlds->capabilities); >
diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index e00ce7f4d0f9..3fbee31995f1 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -529,13 +529,13 @@ int cxl_pci_accel_setup_regs(struct pci_dev *pdev, struct cxl_dev_state *cxlds) int rc; rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map, - cxlds->capabilities); - if (rc) - return rc; - - rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); - if (rc) - return rc; + cxlds->capabilities); + if (!rc) { + rc = cxl_map_device_regs(&map, &cxlds->regs.device_regs); + if (rc) + dev_dbg(&pdev->dev, + "Failed to map device registers.\n"); + } rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &cxlds->reg_map, cxlds->capabilities);
CXL memory device registers provide additional information about device memory and advanced control interface for type-3 device. However, it is not mandatory for a type-2 device. A type-2 device can have HDMs but not CXL memory device registers. Allow a type-2 device not to hanve memory device register when probing CXL registers. Signed-off-by: Zhi Wang <zhiw@nvidia.com> --- drivers/cxl/pci.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)