| Message ID | 20240920223446.1908673-3-zhiw@nvidia.com |
|---|---|
| State | New |
| Headers | show |
| Series | vfio: introduce vfio-cxl to support CXL type-2 accelerator passthrough | expand |
On Fri, 20 Sep 2024 15:34:35 -0700 Zhi Wang <zhiw@nvidia.com> wrote: > CXL core has the information of what CXL register groups a device has. > When initializing the device, the CXL core probes the register groups > and saves the information. The probing sequence is quite complicated. > > vfio-cxl requires the HDM register information to emualte the HDM decoder Hi Zhi, I know these were a bit rushed out so I'll only comment once. Give your patch descriptions a spell check (I always forget :) emulate > registers. > > Introduce cxl_get_hdm_info() for vfio-cxl to leverage the HDM > register information in the CXL core. Thus, it doesn't need to implement > its own probing sequence. > > Signed-off-by: Zhi Wang <zhiw@nvidia.com> > --- > drivers/cxl/core/pci.c | 28 ++++++++++++++++++++++++++++ > drivers/cxl/cxlpci.h | 3 +++ > include/linux/cxl_accel_mem.h | 2 ++ > 3 files changed, 33 insertions(+) > > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c > index a663e7566c48..7b6c2b6211b3 100644 > --- a/drivers/cxl/core/pci.c > +++ b/drivers/cxl/core/pci.c > @@ -502,6 +502,34 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, > } > EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL); > > +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, > + u64 *hdm_reg_offset, u64 *hdm_reg_size) > +{ > + struct pci_dev *pdev = to_pci_dev(cxlds->dev); > + int d = cxlds->cxl_dvsec; > + u16 cap; > + int rc; > + > + if (!cxlds->reg_map.component_map.hdm_decoder.valid) { > + *hdm_reg_offset = *hdm_reg_size = 0; Probably want to zero out the hdm_count as well? > + } else { > + struct cxl_component_reg_map *map = > + &cxlds->reg_map.component_map; > + > + *hdm_reg_offset = map->hdm_decoder.offset; > + *hdm_reg_size = map->hdm_decoder.size; > + } > + > + rc = pci_read_config_word(pdev, > + d + CXL_DVSEC_CAP_OFFSET, &cap); > + if (rc) > + return rc; > + > + *hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); > + return 0; > +} > +EXPORT_SYMBOL_NS_GPL(cxl_get_hdm_info, CXL);
On 17/10/2024 18.44, Jonathan Cameron wrote: > External email: Use caution opening links or attachments > > > On Fri, 20 Sep 2024 15:34:35 -0700 > Zhi Wang <zhiw@nvidia.com> wrote: > >> CXL core has the information of what CXL register groups a device has. >> When initializing the device, the CXL core probes the register groups >> and saves the information. The probing sequence is quite complicated. >> >> vfio-cxl requires the HDM register information to emualte the HDM decoder > Hi Zhi, > > I know these were a bit rushed out so I'll only comment once. > Give your patch descriptions a spell check (I always forget :) > emulate > Thanks for pointing it out. Will proceed. Lol. Me the same. I write a script of sending patches that ask for confirming every item was in the checklist now. >> registers. >> >> Introduce cxl_get_hdm_info() for vfio-cxl to leverage the HDM >> register information in the CXL core. Thus, it doesn't need to implement >> its own probing sequence. >> >> Signed-off-by: Zhi Wang <zhiw@nvidia.com> >> --- >> drivers/cxl/core/pci.c | 28 ++++++++++++++++++++++++++++ >> drivers/cxl/cxlpci.h | 3 +++ >> include/linux/cxl_accel_mem.h | 2 ++ >> 3 files changed, 33 insertions(+) >> >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c >> index a663e7566c48..7b6c2b6211b3 100644 >> --- a/drivers/cxl/core/pci.c >> +++ b/drivers/cxl/core/pci.c >> @@ -502,6 +502,34 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, >> } >> EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL); >> >> +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, >> + u64 *hdm_reg_offset, u64 *hdm_reg_size) >> +{ >> + struct pci_dev *pdev = to_pci_dev(cxlds->dev); >> + int d = cxlds->cxl_dvsec; >> + u16 cap; >> + int rc; >> + >> + if (!cxlds->reg_map.component_map.hdm_decoder.valid) { >> + *hdm_reg_offset = *hdm_reg_size = 0; > Probably want to zero out the hdm_count as well? > >> + } else { >> + struct cxl_component_reg_map *map = >> + &cxlds->reg_map.component_map; >> + >> + *hdm_reg_offset = map->hdm_decoder.offset; >> + *hdm_reg_size = map->hdm_decoder.size; >> + } >> + >> + rc = pci_read_config_word(pdev, >> + d + CXL_DVSEC_CAP_OFFSET, &cap); >> + if (rc) >> + return rc; >> + >> + *hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); >> + return 0; >> +} >> +EXPORT_SYMBOL_NS_GPL(cxl_get_hdm_info, CXL);
diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index a663e7566c48..7b6c2b6211b3 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -502,6 +502,34 @@ int cxl_hdm_decode_init(struct cxl_dev_state *cxlds, struct cxl_hdm *cxlhdm, } EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL); +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, + u64 *hdm_reg_offset, u64 *hdm_reg_size) +{ + struct pci_dev *pdev = to_pci_dev(cxlds->dev); + int d = cxlds->cxl_dvsec; + u16 cap; + int rc; + + if (!cxlds->reg_map.component_map.hdm_decoder.valid) { + *hdm_reg_offset = *hdm_reg_size = 0; + } else { + struct cxl_component_reg_map *map = + &cxlds->reg_map.component_map; + + *hdm_reg_offset = map->hdm_decoder.offset; + *hdm_reg_size = map->hdm_decoder.size; + } + + rc = pci_read_config_word(pdev, + d + CXL_DVSEC_CAP_OFFSET, &cap); + if (rc) + return rc; + + *hdm_count = FIELD_GET(CXL_DVSEC_HDM_COUNT_MASK, cap); + return 0; +} +EXPORT_SYMBOL_NS_GPL(cxl_get_hdm_info, CXL); + #define CXL_DOE_TABLE_ACCESS_REQ_CODE 0x000000ff #define CXL_DOE_TABLE_ACCESS_REQ_CODE_READ 0 #define CXL_DOE_TABLE_ACCESS_TABLE_TYPE 0x0000ff00 diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h index 4da07727ab9c..8d4458f7e45b 100644 --- a/drivers/cxl/cxlpci.h +++ b/drivers/cxl/cxlpci.h @@ -129,4 +129,7 @@ void read_cdat_data(struct cxl_port *port); void cxl_cor_error_detected(struct pci_dev *pdev); pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state); + +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, + u64 *hdm_reg_offset, u64 *hdm_reg_size); #endif /* __CXL_PCI_H__ */ diff --git a/include/linux/cxl_accel_mem.h b/include/linux/cxl_accel_mem.h index 5d715eea6e91..db4182fc1936 100644 --- a/include/linux/cxl_accel_mem.h +++ b/include/linux/cxl_accel_mem.h @@ -55,4 +55,6 @@ struct cxl_region *cxl_create_region(struct cxl_root_decoder *cxlrd, int cxl_region_detach(struct cxl_endpoint_decoder *cxled); int cxl_accel_get_region_params(struct cxl_region *region, resource_size_t *start, resource_size_t *end); +int cxl_get_hdm_info(struct cxl_dev_state *cxlds, u32 *hdm_count, + u64 *hdm_reg_offset, u64 *hdm_reg_size); #endif
CXL core has the information of what CXL register groups a device has. When initializing the device, the CXL core probes the register groups and saves the information. The probing sequence is quite complicated. vfio-cxl requires the HDM register information to emualte the HDM decoder registers. Introduce cxl_get_hdm_info() for vfio-cxl to leverage the HDM register information in the CXL core. Thus, it doesn't need to implement its own probing sequence. Signed-off-by: Zhi Wang <zhiw@nvidia.com> --- drivers/cxl/core/pci.c | 28 ++++++++++++++++++++++++++++ drivers/cxl/cxlpci.h | 3 +++ include/linux/cxl_accel_mem.h | 2 ++ 3 files changed, 33 insertions(+)