From patchwork Mon Oct 7 23:16:24 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ira Weiny X-Patchwork-Id: 13825411 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6504E1DF734; Mon, 7 Oct 2024 23:17:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.8 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728343041; cv=none; b=eYTWfx29LiEoj1puiq2tdscp63JjaBrEqKsficbLutVQ0QhGTk5J2QJrt7YvWdS8gv2URnXaq2H7Z4Q/7ciotnc1QVwuNt0AddYF5yQ2p7zm7SW9XwOM4sIOSwZQAH/pR1VvlAKXmq0X/YlTCvV61NG3fr5zJzPZM9jId5RQ4Pk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728343041; c=relaxed/simple; bh=T4ONxj9Q6toolPyZIZ3ZRAaoin1m2LOEif/CkEOVhDg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CJoCn8ZrunuewUiCfFWWlAa1P9xxuDYbcgpBuK3fy7VA9q6Ch5SyBMAewStmG/1JmHK0DZE53Fla8mzJtLFO/g2Ttl1ZYaclP62RAzXbRiNUQKrGEFovTH2dF3jFyEEWO/uunwoQ0h7KTcPfy2vuyuP3NiuI0C7Q2ecAIb7KYQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=idwr4f05; arc=none smtp.client-ip=192.198.163.8 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="idwr4f05" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1728343039; x=1759879039; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=T4ONxj9Q6toolPyZIZ3ZRAaoin1m2LOEif/CkEOVhDg=; b=idwr4f05BFZB74APVguYysRT0NAs3dd794Bn1VP/2KkYaGZQZbdTjYKM rlzwsqiAIvOpnK3Glk3Jl20tRI/MlNf/n+Ro5UmeEkZDdrN1IHBMuTFMg qT1uY1KhNLQOtt+Xq42cMYq0+9ZjuJdYNqNDD7/Ik4m3NxrlzwIhmTXF8 hbR08NEqDsv5h3XuSnz6KpcY9Yv0Kbv4XtXcucmRzdzX3bhBEFmPa4gks c/GrmeH0Js+bZvLrmkj7JQwaSEJwlw477NFFW+7ho6G04X8LP2TixQLQZ aA7XxqL0FpSc1NJi1DZFlIXjpVwN7PqMzqVT9jmGco2YBmEF3lk0u/rYO w==; X-CSE-ConnectionGUID: 3C9QdA3kT/uck5WR2b5Gpw== X-CSE-MsgGUID: gOXGDgpzRpGhz1WezzuMvA== X-IronPort-AV: E=McAfee;i="6700,10204,11218"; a="45036980" X-IronPort-AV: E=Sophos;i="6.11,185,1725346800"; d="scan'208";a="45036980" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2024 16:17:07 -0700 X-CSE-ConnectionGUID: 7QLL7YquS1aReGhNfIBBJA== X-CSE-MsgGUID: Iwxus2qfSTeQ8YtBermmnA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.11,185,1725346800"; d="scan'208";a="75309185" Received: from ldmartin-desk2.corp.intel.com (HELO localhost) ([10.125.110.112]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Oct 2024 16:17:05 -0700 From: Ira Weiny Date: Mon, 07 Oct 2024 18:16:24 -0500 Subject: [PATCH v4 18/28] cxl/pci: Factor out interrupt policy check Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20241007-dcd-type2-upstream-v4-18-c261ee6eeded@intel.com> References: <20241007-dcd-type2-upstream-v4-0-c261ee6eeded@intel.com> In-Reply-To: <20241007-dcd-type2-upstream-v4-0-c261ee6eeded@intel.com> To: Dave Jiang , Fan Ni , Jonathan Cameron , Navneet Singh , Jonathan Corbet , Andrew Morton Cc: Dan Williams , Davidlohr Bueso , Alison Schofield , Vishal Verma , Ira Weiny , linux-btrfs@vger.kernel.org, linux-cxl@vger.kernel.org, linux-doc@vger.kernel.org, nvdimm@lists.linux.dev, linux-kernel@vger.kernel.org X-Mailer: b4 0.15-dev-37811 X-Developer-Signature: v=1; a=ed25519-sha256; t=1728342968; l=2095; i=ira.weiny@intel.com; s=20221211; h=from:subject:message-id; bh=T4ONxj9Q6toolPyZIZ3ZRAaoin1m2LOEif/CkEOVhDg=; b=Ri1LecsG4XkzHYhbxp+mFk0t/pwfR/hCtw5xySMuXrIHw+2iwhw0gKtFGK/ViRjhjdwk+tC3h vMKWANTbhXdDxLV+U/FEF4nPQrerCsObO2dfyLzaxGjwDu1jKItIdbg X-Developer-Key: i=ira.weiny@intel.com; a=ed25519; pk=noldbkG+Wp1qXRrrkfY1QJpDf7QsOEthbOT7vm0PqsE= Dynamic Capacity Devices (DCD) require event interrupts to process memory addition or removal. BIOS may have control over non-DCD event processing. DCD interrupt configuration needs to be separate from memory event interrupt configuration. Factor out event interrupt setting validation. Reviewed-by: Dave Jiang Reviewed-by: Jonathan Cameron Signed-off-by: Ira Weiny Reviewed-by: Fan Ni --- Changes: [iweiny: reword commit message] [iweiny: keep review tags on simple patch] --- drivers/cxl/pci.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 29a863331bec..c6042db0653d 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -742,6 +742,21 @@ static bool cxl_event_int_is_fw(u8 setting) return mode == CXL_INT_FW; } +static bool cxl_event_validate_mem_policy(struct cxl_memdev_state *mds, + struct cxl_event_interrupt_policy *policy) +{ + if (cxl_event_int_is_fw(policy->info_settings) || + cxl_event_int_is_fw(policy->warn_settings) || + cxl_event_int_is_fw(policy->failure_settings) || + cxl_event_int_is_fw(policy->fatal_settings)) { + dev_err(mds->cxlds.dev, + "FW still in control of Event Logs despite _OSC settings\n"); + return false; + } + + return true; +} + static int cxl_event_config(struct pci_host_bridge *host_bridge, struct cxl_memdev_state *mds, bool irq_avail) { @@ -764,14 +779,8 @@ static int cxl_event_config(struct pci_host_bridge *host_bridge, if (rc) return rc; - if (cxl_event_int_is_fw(policy.info_settings) || - cxl_event_int_is_fw(policy.warn_settings) || - cxl_event_int_is_fw(policy.failure_settings) || - cxl_event_int_is_fw(policy.fatal_settings)) { - dev_err(mds->cxlds.dev, - "FW still in control of Event Logs despite _OSC settings\n"); + if (!cxl_event_validate_mem_policy(mds, &policy)) return -EBUSY; - } rc = cxl_event_config_msgnums(mds, &policy); if (rc)