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Thu, 17 Oct 2024 11:53:16 -0500 From: To: , , , , , , , , CC: Alejandro Lucero Subject: [PATCH v4 04/26] cxl/pci: add check for validating capabilities Date: Thu, 17 Oct 2024 17:52:03 +0100 Message-ID: <20241017165225.21206-5-alejandro.lucero-palau@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20241017165225.21206-1-alejandro.lucero-palau@amd.com> References: <20241017165225.21206-1-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E66:EE_|DM4PR12MB6615:EE_ X-MS-Office365-Filtering-Correlation-Id: e79ac55a-7bfb-495f-046e-08dceecc338a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: n3wKSLLIvP8MQ4KSSj4LsSq64VPPIobjPyBr5iLBG1iMzmQYPY8sHBnYoMODwNbGICHGHGC69X0vEGildZhA+fsVsdEo3u2dwVEUkFdjSIT8R/O0s+t7bCocl+6lyHeVJNLk78gjWlCEBJ7t7irp4HVQb3M3LOJuVuFt2XuO68ccLbviLZ5wpDr4A12YWCJZlVFTbnrlDR25bnw7joCwxiYfk4HWDiEqq/sqmQ1h6WEqVz2Ll/UbzH6ChitAfPa62rT3NoJRCtxUZNoZH+uhKrVDmxPGJByGlFIvIHuqZd11063XrFcF0APVgrbxtjHSwWze8Dm2UtYJiH+s42LmtcXDl7xLTCWMqLM6xVc3+LMGd9RrB42J+9Wv5fiZFrPuSaHG92+q0xvWUV7/sdofSInangLFFT4NgdBudtcI7JvfZyPSo6Z2T8+TkJiPhJzIK8RshpbKJxgZDLNrcThcpQajywyHz0qoedcO9kKY5a6FETzxYCNSihxUMFJ1j4cXYfa9NCBtS33kwoN0pqYmiqsBVeNb31hbT0GvXvVz6kW0QeueZUENtvKaQZA8W3PqJ5QpobB5mY994Tp46JeGcm1GPMXa61XG6PVz+MyA+eoYLd8mT+bsFOz8H7MaNj5wkZtenM2Gtix7bFeickvONDDo2Wdrr5sFPPagSEFO7yMQhnPk9zeEHvcsEb6upaGriAtGSisJ1AN3EI9KW2oXCwa3PB2AtZp0uBKuK1HW0VkPsMpDJdZtIqOKgDOrvPf/Bn4VkXpfEa1bENA7g8T8iW+PMZt6sF99NSwp2zD9yxvhKGK3+rHGx5hE0cH4XibwBlpx7yyefW+l/eLTSHtUXEyN1Qb0hCGfZDMGw/Nx3sKbnGJUvQBucLeBECsZbGN3IA0SMrQfuQc5IZAJl08rcPQDhneOy43QqlKs2h4hEQBIZoymvxjUD4vQMkfLR35Xwf4eIH40eTStGxJXtdGlhBw3lvNwjEppRfJPzFs47NLbqQCbgalm8F4GI9z8SlzqP774b9NaoANzAC67chziiNs91tufiAZ1F/IJncU5B7vkfQrC1vgkzT7GcrVMSmJ835LsLHpMSv8FpyaXMOUIP1NrDfQLcijcrJIwykXCmLh9lxq8vDMPgrhqFpa412yOmdAGr7xoKHd+pEN74evob0Kxe5te8PnfWzCT9GNfdJkYk6yXcqS0/vwXAYUA5j2s8k+pNhJUNzxsgr+kOtzGPB14QxAlLYdLciFqh39BnhjpemWs1sEHryL5eax81JwlmBqAnd6cN5wS34+HfJH/UGAcr4rXfdhMBCnw6SgPJCHUka3dd1FffeQEn2LEYbaQWVaA3mztnUolVczQOFYLKHxnbww0gahU9c6HdqXTzz7E5NuzNcl2tybSWIFYjnsa5vR12WWxHj1t0AW7yodGxw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Oct 2024 16:53:18.4565 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e79ac55a-7bfb-495f-046e-08dceecc338a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E66.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6615 From: Alejandro Lucero During CXL device initialization supported capabilities by the device are discovered. Type3 and Type2 devices have different mandatory capabilities and a Type2 expects a specific set including optional capabilities. Add a function for checking expected capabilities against those found during initialization. Rely on this function for validating capabilities instead of when CXL regs are probed. Signed-off-by: Alejandro Lucero --- drivers/cxl/core/pci.c | 14 ++++++++++++++ drivers/cxl/core/regs.c | 9 --------- drivers/cxl/pci.c | 17 +++++++++++++++++ include/linux/cxl/cxl.h | 3 +++ 4 files changed, 34 insertions(+), 9 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 3d6564dbda57..fa2a5e216dc3 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -1077,3 +1078,16 @@ bool cxl_endpoint_decoder_reset_detected(struct cxl_port *port) __cxl_endpoint_decoder_reset_detected); } EXPORT_SYMBOL_NS_GPL(cxl_endpoint_decoder_reset_detected, CXL); + +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, unsigned long *expected_caps, + unsigned long *current_caps) +{ + if (current_caps) + bitmap_copy(current_caps, cxlds->capabilities, CXL_MAX_CAPS); + + dev_dbg(cxlds->dev, "Checking cxlds caps 0x%08lx vs expected caps 0x%08lx\n", + *cxlds->capabilities, *expected_caps); + + return bitmap_equal(cxlds->capabilities, expected_caps, CXL_MAX_CAPS); +} +EXPORT_SYMBOL_NS_GPL(cxl_pci_check_caps, CXL); diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 9d63a2adfd42..6fbc5c57149e 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -444,15 +444,6 @@ static int cxl_probe_regs(struct cxl_register_map *map, unsigned long *caps) case CXL_REGLOC_RBI_MEMDEV: dev_map = &map->device_map; cxl_probe_device_regs(host, base, dev_map, caps); - if (!dev_map->status.valid || !dev_map->mbox.valid || - !dev_map->memdev.valid) { - dev_err(host, "registers not found: %s%s%s\n", - !dev_map->status.valid ? "status " : "", - !dev_map->mbox.valid ? "mbox " : "", - !dev_map->memdev.valid ? "memdev " : ""); - return -ENXIO; - } - dev_dbg(host, "Probing device registers...\n"); break; default: diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c index 6cd7ab117f80..89c8ac1a61fd 100644 --- a/drivers/cxl/pci.c +++ b/drivers/cxl/pci.c @@ -792,6 +792,8 @@ static int cxl_event_config(struct pci_host_bridge *host_bridge, static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) { struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); + DECLARE_BITMAP(expected, CXL_MAX_CAPS); + DECLARE_BITMAP(found, CXL_MAX_CAPS); struct cxl_memdev_state *mds; struct cxl_dev_state *cxlds; struct cxl_register_map map; @@ -853,6 +855,21 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) if (rc) dev_dbg(&pdev->dev, "Failed to map RAS capability.\n"); + bitmap_clear(expected, 0, BITS_PER_TYPE(unsigned long)); + + /* These are the mandatory capabilities for a Type3 device */ + bitmap_set(expected, CXL_DEV_CAP_HDM, 1); + bitmap_set(expected, CXL_DEV_CAP_DEV_STATUS, 1); + bitmap_set(expected, CXL_DEV_CAP_MAILBOX_PRIMARY, 1); + bitmap_set(expected, CXL_DEV_CAP_DEV_STATUS, 1); + + if (!cxl_pci_check_caps(cxlds, expected, found)) { + dev_err(&pdev->dev, + "Expected capabilities not matching with found capabilities: (%08lx - %08lx)\n", + *expected, *found); + return -ENXIO; + } + rc = cxl_await_media_ready(cxlds); if (rc == 0) cxlds->media_ready = true; diff --git a/include/linux/cxl/cxl.h b/include/linux/cxl/cxl.h index 4a4f75a86018..78653fa4daa0 100644 --- a/include/linux/cxl/cxl.h +++ b/include/linux/cxl/cxl.h @@ -49,4 +49,7 @@ void cxl_set_dvsec(struct cxl_dev_state *cxlds, u16 dvsec); void cxl_set_serial(struct cxl_dev_state *cxlds, u64 serial); int cxl_set_resource(struct cxl_dev_state *cxlds, struct resource res, enum cxl_resource); +bool cxl_pci_check_caps(struct cxl_dev_state *cxlds, + unsigned long *expected_caps, + unsigned long *current_caps); #endif